M38203M4 Datasheet, PDF (113/344 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.2 Interrupts
(4) Processor status register
The processor status register is an 8-bit register. Figure 2.2.13 shows the structure of the processor
status register. Bit 2 related to an interrupt is described below.
sInterrupt disable flag : bit 2
The interrupt disable flag controls the acceptance of interrupt requests except BRK instruction inter-
rupt. When this flag is “1,” the acceptance of an interrupt request is disabled. When this flag is “0,”
the acceptance of an interrupt request is enabled. This flag is set to “1” with the SEI instruction and
is set to “0” with the CLI instruction.
When a main routine branches to an interrupt processing routine, this flag is automatically set to “1,”
so that multiple interrupts are disabled. To use multiple interrupts, set this flag to “0” with the CLI
instruction within the interrupt processing routine.
Processor status register
b7
b2 b0
Undefined 1 ^Unde-
fined
Processor status register (PS)
B
Flag name
0 C : Carry flag
1 Z : Zero flag
2 I : Interrupt disable flag
3 D : Decimal mode flag
4 B : Break flag
5 T : Index X mode flag
6 V : Overflow flag
7 N : Negative flag
b7
b0
indicates initial value immediately after reset
Fig. 2.2.13 Structure of processor status register
3820 GROUP USER’S MANUAL
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