M38203M4 Datasheet, PDF (11/344 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

List of figures
Fig. 53 ICC–f(XIN) characteristic example (VCC = 5.0 V) .................................................................. 1-68
Fig. 54 IOH–VOH characteristic example of CMOS output port at P-channel drive (P0, P1, P3) ..... 1-69
Fig. 55 IOL–VOL characteristic example of CMOS output port at N-channel drive (P0, P1, P3) ...... 1-69
Fig. 56 IOH–VOH characteristic example of CMOS output port at P-channel drive (P2, P5, P6, P7) ... 1-70
Fig. 57 IOL–VOL characteristic example of CMOS output port at N-channel drive (P2, P5, P6, P7) .... 1-70
CHAPTER 2. APPLICATION
Fig. 2.1.1 I/O port write and read ....................................................................................................... 2-2
Fig. 2.1.2 Structure of port Pi (i = 2, 4 to 7) direction register ............................................................ 2-3
Fig. 2.1.3 Structure of ports P0 and P1 direction registers ................................................................ 2-4
Fig. 2.1.4 Port direction register setting example .............................................................................. 2-5
Fig. 2.1.5 Structure of PULL register A ..............................................................................................2-6
Fig. 2.1.6 Structure of PULL register B ..............................................................................................2-6
Fig. 2.1.7 Connection example 1 for key input .................................................................................. 2-8
Fig. 2.1.8 Key input control procedure 1 ............................................................................................ 2-8
Fig. 2.1.9 Timing diagram 1 where switch A is pressed .................................................................... 2-9
Fig. 2.1.10 Connection example 2 for key input .............................................................................. 2-10
Fig. 2.1.11 Key input control procedure 2 ........................................................................................ 2-10
Fig. 2.1.12 Timing diagram 2 where switch A is pressed ................................................................ 2-11
Fig. 2.2.1 Interrupt operation diagram ............................................................................................. 2-15
Fig. 2.2.2 Changes of stack pointer and program counter upon acceptance of interrupt request ... 2-17
Fig. 2.2.3 Processing time up to execution of interrupt processing routine ..................................... 2-18
Fig. 2.2.4 Timing after acceptance of interrupt request ................................................................... 2-18
Fig. 2.2.5 Interrupt control diagram ................................................................................................. 2-19
Fig. 2.2.6 Example of multiple interrupts ......................................................................................... 2-21
Fig. 2.2.7 Memory allocation of interrupt-related registers .............................................................. 2-22
Fig. 2.2.8 Structure of interrupt edge selection register ................................................................... 2-22
Fig. 2.2.9 Structure of interrupt request register 1 ........................................................................... 2-23
Fig. 2.2.10 Structure of interrupt request register 2 ......................................................................... 2-24
Fig. 2.2.11 Structure of interrupt control register 1 .......................................................................... 2-25
Fig. 2.2.12 Structure of interrupt control register 2 .......................................................................... 2-26
Fig. 2.2.13 Structure of processor status register ............................................................................ 2-27
Fig. 2.2.14 Structure of interrupt edge selection register ................................................................. 2-28
Fig. 2.2.15 Connection example when key input interrupt is used, and port P2 block diagram ................................... 2-29
Fig. 2.2.16 Setting values (corresponding to Figure 2.2.15) of key input interrupt-related registers ............................ 2-30
Fig. 2.2.17 Register setting example ............................................................................................... 2-31
Fig. 2.3.1 Timer mode operation example ....................................................................................... 2-33
Fig. 2.3.2 Pulse output mode operation example ............................................................................ 2-35
Fig. 2.3.3 Event counter mode operation example .......................................................................... 2-37
Fig. 2.3.4 Pulse width measurement mode operation example ....................................................... 2-39
Fig. 2.3.5 Timer mode operation example with real time port function ............................................ 2-41
Fig. 2.3.6 Timer mode operation example ....................................................................................... 2-43
Fig. 2.3.7 Period measurement mode operation example ............................................................... 2-45
Fig. 2.3.8 Event counter mode operation example .......................................................................... 2-47
Fig. 2.3.9 Pulse width HL continuously measurement mode operation example ............................ 2-49
Fig. 2.3.10 Memory allocation of timer X- and the timer Y-related registers ................................... 2-50
Fig. 2.3.11 Structure of port P5 direction register ............................................................................ 2-51
Fig. 2.3.12 Structure of port P6 direction register ............................................................................ 2-52
Fig. 2.3.13 Structure of timer X latch ............................................................................................... 2-53
Fig. 2.3.14 Structure of timer X counter ........................................................................................... 2-54
Fig. 2.3.15 Structure of timer Y latch ............................................................................................... 2-55
Fig. 2.3.16 Structure of timer Y counter ........................................................................................... 2-56
Fig. 2.3.17 Structure of timer X mode register ................................................................................. 2-57
Fig. 2.3.18 Structure of timer Y mode register ................................................................................. 2-60
Fig. 2.3.19 Structure of interrupt request register 1 ......................................................................... 2-62
Fig. 2.3.20 Structure of interrupt request register 2 ......................................................................... 2-63
Fig. 2.3.21 Structure of interrupt control register 1 .......................................................................... 2-64
3820 GROUP USER’S MANUAL
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