M38203M4 Datasheet, PDF (12/344 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

List of figures
Fig. 2.3.22 Structure of interrupt control register 2 .......................................................................... 2-65
Fig. 2.3.23 Example of setting registers for using timer mode ........................................................ 2-66
Fig. 2.3.24 Example of setting registers for using pulse output mode ............................................. 2-67
Fig. 2.3.25 Example of setting registers for using event counter mode ........................................... 2-68
Fig. 2.3.26 Example of setting registers for using pulse width measurement mode ....................... 2-69
Fig. 2.3.27 Example of setting registers for using RTP ................................................................... 2-70
Fig. 2.3.28 Example of setting registers for using timer mode ........................................................ 2-71
Fig. 2.3.29 Example of setting registers for using period measurement mode ............................... 2-72
Fig. 2.3.30 Example of setting registers for using event counter mode ........................................... 2-73
Fig. 2.3.31 Example of setting registers for using pulse width HL continuously measurement mode .......................... 2-74
Fig. 2.3.32 Example of peripheral circuit ......................................................................................... 2-75
Fig. 2.3.33 Connection of timer and setting of division ratio ............................................................ 2-75
Fig. 2.3.34 Setting of related registers ............................................................................................. 2-76
Fig. 2.3.35 Control procedure ..........................................................................................................2-76
Fig. 2.3.36 Example of peripheral circuit ......................................................................................... 2-77
Fig. 2.3.37 Setting of related registers ............................................................................................. 2-77
Fig. 2.3.38 Ringer signal waveform ................................................................................................. 2-78
Fig. 2.3.39 Operation timing when ringing pulse is input ................................................................. 2-78
Fig. 2.3.40 Control procedure ..........................................................................................................2-79
Fig. 2.3.41 Application connection example when RTP is used ...................................................... 2-80
Fig. 2.3.42 RTP output example ...................................................................................................... 2-80
Fig. 2.3.43 Timer X interrupt processing procedure example when RTP is used ........................... 2-81
Fig. 2.4.1 Timer mode operation example ....................................................................................... 2-86
Fig. 2.4.2 Rewriting example of counter and latch corresponding to timers 1 or 3 .......................... 2-87
Fig. 2.4.3 Rewriting example of timer 2 counter and timer 2 latch (Writing in timer 2 latch only) .... 2-88
Fig. 2.4.4 Pulse output example ...................................................................................................... 2-89
Fig. 2.4.5 Memory allocation of timer-related registers ................................................................... 2-90
Fig. 2.4.6 Structure of latches ..........................................................................................................2-91
Fig. 2.4.7 Structure of timer counters .............................................................................................. 2-92
Fig. 2.4.8 Structure of timer 123 mode register ............................................................................... 2-93
Fig. 2.4.9 Structure of interrupt request register 1 ........................................................................... 2-95
Fig. 2.4.10 Structure of interrupt request register 2 ......................................................................... 2-96
Fig. 2.4.11 Structure of interrupt control register 1 .......................................................................... 2-97
Fig. 2.4.12 Structure of interrupt control register 2 .......................................................................... 2-98
Fig. 2.4.13 Example of setting registers for timers 1, 2, and 3 ........................................................ 2-99
Fig. 2.4.14 Setting of related registers ........................................................................................... 2-100
Fig. 2.4.15 Control procedure ........................................................................................................2-101
Fig. 2.5.1 External connection example in clock synchronous mode ............................................ 2-103
Fig. 2.5.2 Shift clock ......................................................................................................................2-104
Fig. 2.5.3 Transmit operation in clock synchronous mode ............................................................ 2-107
Fig. 2.5.4 Transmit timing example in clock synchronous mode ................................................... 2-108
Fig. 2.5.5 Receive operation in clock synchronous mode ............................................................. 2-110
Fig. 2.5.6 Receive timing example in clock synchronous mode .................................................... 2-110
Fig. 2.5.7 Transmit/receive timing example in clock synchronous mode ...................................... 2-111
Fig. 2.5.8 External connection example in UART mode ................................................................ 2-112
Fig. 2.5.9 Transfer data format in UART mode .............................................................................2-114
Fig. 2.5.10 All transfer data formats in UART mode ......................................................................2-115
Fig. 2.5.11 Transmit timing example in UART mode ..................................................................... 2-117
Fig. 2.5.12 Receive timing example in UART mode ......................................................................2-119
Fig. 2.5.13 Memory allocation of serial I/O1-related registers ....................................................... 2-121
Fig. 2.5.14 Structure of transmit/receive buffer register ................................................................ 2-121
Fig. 2.5.15 Structure of serial I/O1 status register ......................................................................... 2-122
Fig. 2.5.16 Structure of serial I/O1 control register ........................................................................ 2-124
Fig. 2.5.17 Structure of UART control register .............................................................................. 2-127
Fig. 2.5.18 Transmitting method in clock synchronous mode (1) .................................................. 2-129
Fig. 2.5.19 Transmitting method in clock synchronous mode (2) .................................................. 2-130
Fig. 2.5.20 Receiving method in clock synchronous mode (1) ...................................................... 2-131
Fig. 2.5.21 Receiving method in clock synchronous mode (2) ...................................................... 2-132
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3820 GROUP USER’S MANUAL