M38203M4 Datasheet, PDF (38/344 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMERS
The 3820 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “0016”,
an underflow occurs at the next count pulse and the correspond-
ing timer latch is reloaded into the timer and the count is contin-
ued. When a timer underflows, the interrupt request bit corre-
sponding to that timer is set to “1”.
Read and write operation on 16-bit timer must be performed for
both high and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write the
low-order byte first. The 16-bit timer cannot perform the correct op-
eration when reading during the write operation, or when writing
during the read operation.
Real time port
control bit "1"
QD
P60
P60 data for real time port
Data bus
P60 direction register "0"
Latch
P60 latch
Real time port
control bit
"1"
QD
P61
P61 direction register "0"
Latch
P61 latch
f(XIN)/16
(f(XCIN)/16 in low-speed mode*)
P54/CNTR0
CNTR0 active
edge switch bit
"0"
Timer X operat-
ing mode bit
"00","01","11"
"10"
"1"
Pulse width
measurement
mode CNTR0 active
edge switch bit "0"
P54 direction register
"1"
P54 latch
P61 data for real time port
Real time port
control bit "0"
"1"
Timer X mode register
write signal
Timer X stop
control bit
Timer X write
control bit
Timer X (low) latch (8) Timer X (high) latch (8)
Timer X (low) (8)
Timer X (high) (8)
QS
T
Q
Pulse output mode
Timer Y operating mode bit
"00","01","10"
Pulse width HL continuously measurement mode
Rising edge detection
"11"
Pulse output mode
Falling edge detection
Period
measurement mode
f(XIN)/16
(f(XCIN)/16 in low-speed mode*)
Timer Y stop
CNTR1 active
control bit
P55/CNTR1
edge switch bit _{"00","01","11"}
"0"
Timer Y (low) latch (8) Timer Y (high) latch (8)
Timer Y (low) (8)
Timer Y (high) (8)
"10"Timer Y operating
"1"
mode bit
f(XIN)/16
(f(XCIN)/16 in low-speed mode*)
Timer 1 count source
selection bit
"0"
XCIN
"1"
Timer 1 latch (8)
Timer 1 (8)
Timer 2 count source
selection bit
"0"
Timer 2 latch (8)
Timer 2 (8)
"1"
f(XIN)/16
(f(XCIN)/16 in low-speed mode*)
Timer 2 write
control bit
Timer X
interrupt
request
CNTR0
interrupt
request
CNTR1
interrupt
request
Timer Y
interrupt
request
Timer 1
interrupt
request
Timer 2
interrupt
request
P56/TOUT
P56 direction register
TOUT output
active edge
switch bit "0"
TOUT output
control bit
QS
"1"
P56 latch
T
Q
TOUT output control bit
f(XIN)/16(f(XCIN)/16 in low-speed mode*)
* Internal clock φ = XCIN/2.
Timer 3 latch (8)
"0"
Timer 3 (8)
"1"
Timer 3 count
source selection
bit
Timer 3
interrupt
request
Fig. 18 Timer block diagram
1-22
3820 GROUP USER’S MANUAL