M38203M4 Datasheet, PDF (43/344 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Asynchronous Serial I/O1 (UART) Mode
Clock asynchronous serial I/O1 mode (UART) can be selected by
clearing the serial I/O1 mode selection bit of the serial I/O1 control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer regis-
ter, but the two buffers have the same address in memory. Since
the shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer register, and receive data is
read from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
P44/RXD
P46/SCLK1
f(XIN)
P45/TXD
Data bus
Address 001816
Serial I/O1 control register Address 001A16
OE
Receive buffer register(RB)
Character length selection bit
Receive buffer full flag (RBF)
Serial I/O receive interrupt request (RI)
STdetector 7 bits
Receive shift register
8 bits
1/16
PE FE SP detector
Clock control circuit
UART control register
Address 001B16
Serial I/O1 synchronization clock selection bit
BRG count source selection bit
1/4
Frequency division ratio 1/(n+1)
Baud rate generator
Address 001C16
ST/SP/PA generator
1/16
Transmit shift register shift completion flag (TSC)
Character length selection bit
Transmit shift register
Transmit interrupt source selection bit
Serial I/O1 status register
Transmit buffer register
Address 001816
Transmit buffer empty flag (TBE)
Serial I/O1 status register Address 001916
Data bus
Fig. 24 Block diagram of UART serial I/O1
Transmit or receive clock
Transmit buffer register
write signal
TBE=0
TSC=0
TBE=1
Serial output TXD
ST
Receive buffer register
read signal
TBE=0
D0
D1
1 start bit
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit (s)
Serial input RXD
ST
D0
D1
TBE=1
SP
ST
D0
TSC=1^V
D1
SP
V _{Generated at 2nd bit in 2-stop-bit mode}
RBF=1
SP
ST
RBF=0
D0
D1
RBF=1
SP
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception).
2: The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt
source selection bit (TIC) of the serial I/O1 control register.
3: The serial I/O1 receive interrupt (RI) is set when the RBF flag becomes "1".
4: After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 25 Operation of UART serial I/O1 function
3820 GROUP USER’S MANUAL
1-27