M38203M4 Datasheet, PDF (148/344 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.3 Timer X and timer Y
(7) Interrupt request register 1 (IREQ1) and interrupt request register 2 (IREQ2)
The interrupt request register 1 (address 003C16) and the interrupt request register 2 (address 003D16)
indicate whether an interrupt request has occured or not.
Figure 2.3.19 shows the structure of the interrupt request register 1 and Figure 2.3.20 shows the
structure of the interrupt request register 2.
The occurrence of an interrupt request (timer X, timer Y, CNTR0, and CNTR1 interrupt requests)
causes the corresponding bit to be set to “1.” This interrupt request bit is automatically cleared to “0”
by the acceptance of the interrupt request.
The interrupt request bits can be set to “0” by software, but it cannot be set to “1” by software.
The occurrence of each interrupt is controlled by the corresponding interrupt enable bit (refer to the
next item).
For details of interrupts, refer to “2.2 Interrupts.”
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address 3C16]
B
Name
0 INT0 interrupt request
bit
1 INT1 interrupt request
bit
2 Serial I/O1 receive
interrupt request bit
3 ^{Serial I/O1 transmit}
interrupt request bit
4 Timer X interrupt
request bit
5 Timer Y interrupt
request bit
6 ^{Timer 2 interrupt}
request bit
7 Timer 3 interrupt
request bit
Functions
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
At reset R W
0
V
0
V
0
V
0
V
0
V
0
V
0
V
0
V
V : “0” can be set by software, but “1” cannot be set.
Fig. 2.3.19 Structure of interrupt request register 1
2–62
3820 GROUP USER’S MANUAL