M38203M4 Datasheet, PDF (195/344 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.5 Serial I/O1
sReceive operation in the clock synchronous mode
Receive operation in the clock synchronous mode is described below.
qStart of receive operation
A receive operation is started by writing the following data into the receive buffer register (address
001816) in the receive enable state.^V1
•Transmit data in the full duplex data transfer mode
•Arbitrary dummy data in the half duplex data transfer mode
qReceive operation
ŒEach 1-bit data is read into the receive shift
register from the P44/RxD pin in synchroni-
zation with the rising of the shift clocks.
D1
P44/RxD
b0
D0
Receive shift register
The data enters first into the most significant
bit of the receive shift register. Each time 1-
bit data is received, the data of the receive
shift register is shifted by 1 bit toward the
least significant bit.
ŽWhen 1-byte data has been input into the
receive shift register, the data of the receive
shift register is transferred to the receive buffer
register (address 001816).^V2
D4
P44/RxD
b0
D3 D2 D1 D0
Receive shift register
Receive shift register D7 D6 D5 D4 D3 D2 D1 D0
Transfer receive data
[Address 1816] Receive buffer register
When a data transfer to the receive buffer
register is completed, the receive buffer full
Serial I/O1 status
register
0
flag (bit 1) of the serial I/O1 status register
[Address 1916]
1
(address 001916) is set to “1,”^V3 a serial I/O1
b1
receive interrupt request occurs.
V1: Initialization of register or others for a re-
ceive operation. Refer to “2.5.4 Register
setting example.”
V2: When data remains without reading out the data of the receive buffer register (the receive buffer
full flag is “1”) and yet all the receive data has been input to the receive shift register, the overrun
error flag of the serial I/O1 status register is set to “1.” At this time, the data of the receive shift
register is not transferred to the receive buffer register, but the former data of the receive buffer
register is held.
V3: The receive buffer full flag is cleared to “0” by reading out the receive buffer register.
3820 GROUP USER’S MANUAL
2–109