M38203M4 Datasheet, PDF (208/344 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.5 Serial I/O1
(2) Serial I/O1 status register (SIO1STS)
This register (address 001916) consists of the following flags:
•flags representing the states of the registers used for transmission/reception
•error flags.
This is a read-only register.
Bit 7 is unused and set to “1” at reading.
Serial I/O1 status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 status register (SIO1STS) [Address 1916]
B
Name
Functions
At reset R W
0 _{Transmit buffer}
0: Buffer full
0
×
empty flag (TBE)
1: Buffer empty
1 Receive buffer full flag 0: Buffer empty
(RBF)
1: Buffer full
0
×
2 Transmit shift register shift 0: Transmit shift in progress 0
×
completion flag (TSC)
1: Transmit shift completed
3 ^{Overrun error flag}
(OE)
0: No error
1: Overrun error
0
×
4 Parity error flag
(PE)
0: No error
1: Parity error
0
×
5 ^{Framing error flag}
(FE)
0: No error
1: Framing error
0
×
6 ^{Summing error flag 0: (OE) U (PE) U (FE) = 0}
0
×
(SE)
1: (OE) U (PE) U (FE) = 1
7 Nothing is allocated. This bit cannot be written to
and is fixed to “1” at reading.
1 1^×
Fig. 2.5.15 Structure of serial I/O1 status register
sTransmit buffer empty flag (bit 0)
This flag is automatically cleared to “0” by writing transmit data into the transmit buffer register.
After the transmit data is written in the transmit buffer register, it is transferred to the transmit shift
register. When this transfer is completed and the transmit buffer register becomes empty, this flag is
automatically is set to “1.”
It is possible to write transmit data into the transmit buffer register only while the transmit buffer empty
flag is “1.”
This flag is valid in both the clock synchronous mode and the UART mode.
sReceive buffer full flag (bit 1)
When all receive data has been input to the receive shift register and then this receive data is
transferred to the receive buffer register, this flag is automatically is set to “1.”
When the transferred receive data is read out from the receive buffer register, the flag is automatically
is cleared to “0.”
If all the next receive data is input to the receive shift register when the receive buffer flag is “1” (the
receive buffer register is not yet read out), the overrun error flag is set to “1.”
This flag is valid in both the clock synchronous mode and the UART mode.
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3820 GROUP USER’S MANUAL