M38203M4 Datasheet, PDF (13/344 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

List of figures
Fig. 2.5.22 Transmitting method in UART mode (1) ......................................................................2-133
Fig. 2.5.23 Transmitting method in UART mode (2) ......................................................................2-134
Fig. 2.5.24 Receiving method in UART mode (1) .......................................................................... 2-135
Fig. 2.5.25 Receiving method in UART mode (2) .......................................................................... 2-136
Fig. 2.6.1 External connection example of serial I/O2 ................................................................... 2-141
Fig. 2.6.2 Shift clock ......................................................................................................................2-142
Fig. 2.6.3 Transmit operation of serial I/O2 ...................................................................................2-144
Fig. 2.6.4 Transmit timing example of serial I/O2 .......................................................................... 2-144
Fig. 2.6.5 Receive operation of serical I/O2 ..................................................................................2-146
Fig. 2.6.6 Receive timing example of serial I/O2 ........................................................................... 2-146
Fig. 2.6.7 Transmit/receive timing example of serial I/O2 (P53/SRDY2 pin is used) ....................... 2-147
Fig. 2.6.8 Memory allocation of serial I/O2-related registers ......................................................... 2-149
Fig. 2.6.9 Structure of serial I/O2 control register .......................................................................... 2-149
Fig. 2.6.10 Structure of serial I/O2 register ....................................................................................2-151
Fig. 2.6.11 Transmitting method of serial I/O2 .............................................................................. 2-152
Fig. 2.6.12 Receiving method of serial I/O2 ..................................................................................2-153
Fig. 2.7.1 Memory allocation of LCD display-related registers ...................................................... 2-159
Fig. 2.7.2 Structure of segment output enable register ................................................................. 2-160
Fig. 2.7.3 Structure of LCD mode register ..................................................................................... 2-162
Fig. 2.7.4 Structure of port P0 direction register ............................................................................2-163
Fig. 2.7.5 Structure of port P1 direction register ............................................................................2-164
Fig. 2.7.6 Structure of PULL register A ..........................................................................................2-165
Fig. 2.7.7 Example of setting registers for LCD display (1) ........................................................... 2-166
Fig. 2.7.8 Example of setting registers for LCD display (2) ........................................................... 2-167
Fig. 2.7.9 8-segment LCD panel display pattern example when the duty ratio number is 4 ......... 2-168
Fig. 2.7.10 LCD panel example .....................................................................................................2-169
Fig. 2.7.11 Segment allocation example ....................................................................................... 2-169
Fig. 2.7.12 LCD display RAM setting example .............................................................................. 2-169
Fig. 2.7.13 Setting of related registers ........................................................................................... 2-170
Fig. 2.7.14 Control procedure ........................................................................................................2-171
Fig. 2.8.1 Internal reset signal output timing ..................................................................................2-173
Fig. 2.8.2 Structure of watchdog timer control register .................................................................. 2-175
Fig. 2.9.1 Oscillation stabilizing time at restoration by reset input ................................................. 2-177
Fig. 2.9.2 Execution sequence example at restoration by occurrence of INT0 interrupt request .. 2-179
Fig. 2.9.3 Reset input time .............................................................................................................2-182
Fig. 2.9.4 State transitions of internal clock φ ......................................................................................... 2-184
Fig. 2.10.1 Internal reset state hold/release timing ........................................................................ 2-185
Fig. 2.10.2 Internal processing sequence immediately after reset release ................................... 2-186
Fig. 2.10.3 Internal state of microcomputer immediately after reset release ................................. 2-187
Fig. 2.10.4 Poweron reset conditions ............................................................................................ 2-188
Fig. 2.10.5 Poweron reset circuit examples ...................................................................................2-188
Fig. 2.11.1 Oscillation circuit example using ceramic resonators .................................................. 2-190
Fig. 2.11.2 External clock input circuit example ............................................................................2-191
Fig. 2.11.3 Clock generating circuit block diagram ........................................................................ 2-192
Fig. 2.11.4 Structure of φ output control register ........................................................................... 2-193
Fig. 2.11.5 State transitions of internal clock φ ...................................................................................... 2-196
Fig. 2.11.6 Oscillation stabilizing time at poweron ......................................................................... 2-197
Fig. 2.11.7 Oscillation stabilizing time at reoscillation of XIN ....................................................................... 2-198
3820 GROUP USER’S MANUAL
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