M38203M4 Datasheet, PDF (163/344 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.3 Timer X and timer Y
(2) Pulse width measurement mode: Ringer signal detection
Outline : A telephone ringing pulse^V is detected by applying the timer X interrupt and the pulse width
measurement mode.
Specifications : •Whether a telephone call exists or not is judged by measuring a pulse width output
from the “H” active ringing pulse detection circuit.
•f(XIN) = 8 MHz is used as the count source.
•When the following condition is satisfied, it is regard as normal.
200 ms ≤ pulse width of a ringing pulse < 1.2 s
Figure 2.3.36 shows an example of a peripheral circuit, Figure 2.3.37, the setting of the related
registers, Figure 2.3.38, a ringing pulse waveform, Figure 2.3.39, an operation timing when a ringing
pulse is input, and Figure 2.3.40, the control procedure.
3820 group
CNTR0
Ringing pulse
detection
circuit
Telephone circuit
V Ringing pulse : _{Signal which is sent by turning on/off (make/break) the telephone line.}
Each country has a different standard. In this case, Japanese domestic
standard is adopted as an example.
Fig. 2.3.36 Example of peripheral circuit
b7
b0
X X X 0 X X X X P5D : Port P5 direction register [Address 0B16]
b4 : Bit corresponding to port P54
0 : Input mode
b7
b0
1 0 1 1 X X X X _{TXM : Timer X mode register [Address 2716]}
b5, b4 : Timer X operating mode bits
1 1 : Pulse width measurement mode
b6 : CNTR0 active edge switch bit
0 : •Pulse width measurement mode (Measure “H” level width)
•CNTR0 interrupt (Falling edge active)
b7 : Timer X stop control bit
1 : Count stop
A716
TXL : Timer X (low-order) [Address 2016]
6116
TXH : Timer X (high-order) [Address 2116]
Set “division ratio – 1 (24999 : 61A716) ” in the timer X register
Note : Write values in the order of
the low-order byte and the
high-order byte.
b7
b0
X X X 1 X X X X ICON1 : Interrupt control register 1 [Address 3E16]
b4 : Timer X interrupt enable bit
1 : Interrupt enabled
b7
b0
0 X X X X X X 1 ICON2 : Interrupt control register 2 [Address 3F16]
b0 : CNTR0 interrupt enable bit
1 : Interrupt enabled
Fig. 2.3.37 Setting of related registers
3820 GROUP USER’S MANUAL
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