M38203M4 Datasheet, PDF (177/344 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.4 Timer 1, timer 2, and timer 3
(1) Timer latches and timer counters (corresponding to timers 1 to 3)
The latches and the counters each consist of 8 bits and are allocated at the same address for each
timer.
To access a latch and a counter, access the corresponding timer. When the timer is read out, the
value of the counter (count value) is read out.
sLatch
The latch is a register which holds the value to be transferred (reloaded) automatically to the counter
as the initial value of the counter at the counter underflow. It is impossible to read out the value of
the latch. Figure 2.4.6 the structure of the latches.
For the rewrite operation of the value of the latch, refer to “2.4.1 Explanation of operations, (2)
Rewriting the value of the counter and the latch.”
qTimer 1 latch and timer 3 latch
Timer 1 and timer 3
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1 and timer 3 (T1,T3) [Address 2416, 2616]
B
Functions
At reset R W
0 ^{•Set “0016 to FF16” as timers 1 or 3 count value.} 1 ^×
to ^{•The values of each timer are set to the}
7 ^{respective latches and transferred auto-}
matically to the respective counters at the
counter underflow.
qTimer 2 latch
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2 (T2) [Address 2516]
B
Functions
0 •Set “0016 to FF16” as timer 2 count value.
•The value of timer 2 is set to the timer 2
latch and transferred automatically to the
1 _{timer 2 counter at the timer 2 counter}
to _underflow.
7
At reset R W
1^×
0^×
Fig. 2.4.6 Structure of latches
3820 GROUP USER’S MANUAL
2–91