M38203M4 Datasheet, PDF (206/344 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.5 Serial I/O1
2.5.2 Pins
The serial I/O1 uses 4 pins, namely, pins for data transmit, data receive, shift clock transmit/receive, and
receive enable signal output. All these pins are also used as port P4 and switched their functions by the
serial I/O1 enable bit (bit 7) and SRDY1 output enable bit (bit 2) of the serial I/O1 control register (address
001A16).
The function of each pin is described below.
(1) Data transmit pin [TxD]
This pin outputs each bit of transmit data and is used as port P45.
When the serial I/O1 enable bit of the serial I/O1 control register is set to “1,” this pin functions as
a serial I/O1 data output pin.
(2) Data receive pin [RxD]
This pin inputs each bit of receive data and is used as port P44.
When the serial I/O1 enable bit of the serial I/O1 control register is set to “1,” this pin functions as
a serial I/O1 data input pin.
(3) Shift clock transmit/receive pin [SCLK1]
sClock synchronous mode
This pin inputs (receives from the outside) or outputs (supplies to the outside) a shift clock used for
transmission and reception.
When the serial I/O1 synchronization clock selection bit (bit 1) of the serial I/O1 control register is set
to “0” (use of internal clock), a shift clock is output to the outside. When this bit is set to “1” (use of
external clock), a shift clock is input from the outside.
sUART mode
When the serial I/O1 synchronization clock selection bit (bit 1) of the serial I/O1 control register is set
to “1” (use of external clock), a shift clock is supplied from the outside. When this bit is set to “0” (use
of internal clock), this pin does not function.
(4) Receive enable signal output pin [SRDY1]
This pin notifies the outside of the receive enable state in the clock synchronous mode. This pin does
not function in the UART mode.
•The SRDY1 output enable bit (bit 2) of the serial I/O1 control register is set to “1.”
•The transmit enable bit (bit 4) of the serial I/O1 control register is set to “1.”
When the above two conditions are satisfied, the pin level changes from “H” to “L” at the timing which
data is written into the receive buffer register, notifying the outside of the receive enable state.
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3820 GROUP USER’S MANUAL