M38203M4 Datasheet, PDF (247/344 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.7 LCD drive control circuit
(2) LCD mode register (LM)
The LCD mode register (address 003916) controls various functions of the LCD controller/driver.
Figure 2.7.3 shows the structure of the LCD mode register.
qBits 0, 1
: Duty ratio selection bits
Select a duty ratio number fit for the LCD panel used.
qBit 2
: Bias control bit
Select a bias value fit for the LCD panel used.
qBit 3
: LCD enable bit
Turns on and off the LCD. When this bit is set to “1,” the bits which are set to “1”
in the LCD display RAM are displayed on the LCD. When this bit is set to “0,” the
whole LCD display is turned off.
qBit 4
: Unused
Always set this bit to “0.”
qBits 5, 6
: LCD circuit divider division ratio selection bits
These bits are used to select a division ratio for generating the frequency of the
LCDCK, which is the clock for the LCD timing controller. Select a division ratio so
as to generate LCDCK fit for the LCD panel used.
qBit 7
: LCDCK count source selection bit
This bit is used to select a count source of the above LCDCK. At transition from
the high-speed, middle-speed or low-speed mode to the low-power operation, or
others, change the count source as required.
3820 GROUP USER’S MANUAL
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