M38203M4 Datasheet, PDF (183/344 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.4 Timer 1, timer 2, and timer 3
(4) Interrupt control register 1 (ICON1) and interrupt control register 2 (ICON2)
The interrupt control register 1 (address 003E16) and the interruot contorol register 2 (address 003F16)
control each interrupt request source.
Figure 2.4.11 shows the structure of the interrupt control register 1 and Figure 2.4.12 shows the
structure of the interrupt control register 2.
When an interrupt enable bit is “0,” the corresponding interrupt request is disabled. If an interrupt
request occurs when this bit is “0,” the corresponding interrupt request bit only is set to “1,” and the
interrupt request is not accepted.
When the interrupt enable bit is “1,” the corresponding interrupt request is enabled. If an interrupt
request occurs when this bit is “1,” the interrupt request is accepted (interrupt disable flag = “0”).
Each interrupt enable bit can be set to “0” or “1” by software.
For details of interrupts, refer to “2.2 Interrupts.”
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address 3E16]
B
Name
0 INT0 interrupt enable
bit
1 INT1 interrupt enable
bit
2 ^{Serial I/O1 receive}
interrupt enable bit
3 ^{Serial I/O1 transmit}
interrupt enable bit
4 Timer X interrupt
enable bit
5 Timer Y interrupt
enable bit
6 ^{Timer 2 interrupt}
enable bit
7 Timer 3 interrupt
enable bit
Functions
0 : Interrupts disabled
1 : Interrupts enabled
0 : Interrupts disabled
1 : Interrupts enabled
0 : Interrupts disabled
1 : Interrupts enabled
0 : Interrupts disabled
1 : Interrupts enabled
0 : Interrupts disabled
1 : Interrupts enabled
0 : Interrupts disabled
1 : Interrupts enabled
0 : Interrupts disabled
1 : Interrupts enabled
0 : Interrupts disabled
1 : Interrupts enabled
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.4.11 Structure of interrupt control register 1
3820 GROUP USER’S MANUAL
2–97