M38203M4 Datasheet, PDF (251/344 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.7 LCD drive control circuit
(5) PULL register A (PULLA)
When ports P0, P1 and P3 are set for the input mode, the setting of bits 0, 1 and 3 of the PULL
register A (address 001616) is valid.
The pull-down function of ports P0, P1 and P3 is made effective by setting bits 0, 1 and 3 of the PULL
register A to “1.” When ports P0 and P1 are set for output mode by bit 0 of the port P0/P1 direction
registers, the setting of the PULL register A is invalid.
Figure 2.7.6 shows the structure of the PULL register A.
PULL register A
b7 b6 b5 b4 b3 b2 b1 b0
PULL register A (PULLA) [Address 1616]
B
Name
Function
0 Ports P00–P07 pull-down bit ^{0 : No pull-down}
1 : Pull-down
1 Ports P10–P17 pull-down bit ^{0 : No pull-down}
1 : Pull-down
2 _{Ports P20–P27 pull-up bit}
0 : No pull-up
1 : Pull-up
3 Ports P30–P37 pull-down bit 0 : No pull-down
1 : Pull-down
4 Ports P70, P71 pull-up bit
0 : No pull-up
1 : Pull-up
5 _{Nothing is allocated. These bits cannot be}
to _{written to and are fixed to “0” at reading.}
7
At reset R W
1
1
0
1
0
0 ^0×
Note: For ports set for the output mode, pull-up or pull-down is
impossible.
Fig. 2.7.6 Structure of PULL register A
3820 GROUP USER’S MANUAL
2–165