PIC18FXX39 Datasheet, PDF (91/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

9.4 PORTD, TRISD and LATD
Registers
This section is applicable only to the PIC18F4X39
devices.
PORTD is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a High Impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register reads and writes the latched output value for
PORTD.
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output.
Note: On a Power-on Reset, these pins are
configured as digital inputs.
PORTD can be configured as an 8-bit wide micropro-
cessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mode, the input buffers
are TTL. See Section 9.6 for additional information on
the Parallel Slave Port (PSP).
EXAMPLE 9-4: INITIALIZING PORTD
CLRF PORTD
CLRF LATD
MOVLW 0xCF
MOVWF TRISD
; Initialize PORTD by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
PIC18FXX39
FIGURE 9-8:
PORTD BLOCK DIAGRAM
IN I/O PORT MODE
RD LATD
Data
Bus
WR LATD
or PORTD
WR TRISD
D
Q
CK
Data Latch
DQ
CK
TRIS Latch
RD TRISD
I/O pin⁽¹⁾
Schmitt
Trigger
Input
Buffer
RD PORTD
Q
D
ENEN
Note 1: I/O pins have diode protection to VDD and VSS.
 2002-2013 Microchip Technology Inc.
Preliminary
DS30485B-page 91