PIC18FXX39 Datasheet, PDF (27/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

PIC18FXX39
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
FSR1H
2439 4439 2539 4539
---- xxxx
---- uuuu
---- uuuu
FSR1L
2439 4439 2539 4539
xxxx xxxx
uuuu uuuu
uuuu uuuu
BSR
2439 4439 2539 4539
---- 0000
---- 0000
---- uuuu
INDF2
2439 4439 2539 4539
N/A
N/A
N/A
POSTINC2 2439 4439 2539 4539
N/A
N/A
N/A
POSTDEC2 2439 4439 2539 4539
N/A
N/A
N/A
PREINC2 2439 4439 2539 4539
N/A
N/A
N/A
PLUSW2 2439 4439 2539 4539
N/A
N/A
N/A
FSR2H
2439 4439 2539 4539
---- xxxx
---- uuuu
---- uuuu
FSR2L
2439 4439 2539 4539
xxxx xxxx
uuuu uuuu
uuuu uuuu
STATUS
2439 4439 2539 4539
---x xxxx
---u uuuu
---u uuuu
TMR0H
2439 4439 2539 4539
0000 0000
uuuu uuuu
uuuu uuuu
TMR0L
2439 4439 2539 4539
xxxx xxxx
uuuu uuuu
uuuu uuuu
T0CON
OSCCON^*
2439 4439 2539 4539
2439 4439 2539 4539
1111 1111
---- ---0
1111 1111
---- ---0
uuuu uuuu
---- ---u
LVDCON 2439 4439 2539 4539
--00 0101
--00 0101
--uu uuuu
WDTCON 2439 4439 2539 4539
---- ---0
---- ---0
---- ---u
RCON⁽⁴⁾
2439 4439 2539 4539
0--q 11qq
0--q qquu
u--u qquu
TMR1H
2439 4439 2539 4539
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1L
2439 4439 2539 4539
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
TMR2^*
PR2^*
T2CON^*
2439 4439 2539 4539
2439 4439 2539 4539
2439 4439 2539 4539
2439 4439 2539 4539
0-00 0000
0000 0000
1111 1111
-000 0000
u-uu uuuu
0000 0000
1111 1111
-000 0000
u-uu uuuu
uuuu uuuu
1111 1111
-uuu uuuu
SSPBUF
2439 4439 2539 4539
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPADD
2439 4439 2539 4539
0000 0000
0000 0000
uuuu uuuu
SSPSTAT 2439 4439 2539 4539
0000 0000
0000 0000
uuuu uuuu
SSPCON1 2439 4439 2539 4539
0000 0000
0000 0000
uuuu uuuu
SSPCON2 2439 4439 2539 4539
0000 0000
0000 0000
uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
* These registers are retained to maintain compatibility with PIC18FXX2 devices; however, one or more bits
are reserved. Users should not modify the value of these bits. See Section 4.9.2 for details.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
Oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
 2002-2013 Microchip Technology Inc.
Preliminary
DS30485B-page 27