PIC18FXX39 Datasheet, PDF (207/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

PIC18FXX39
FIGURE 20-3:
CODE PROTECTED PROGRAM MEMORY FOR PIC18FXX39
MEMORY SIZE/DEVICE
16 Kbytes
(PIC18FX439)
32 Kbytes
(PIC18FX539)
Boot Block
Boot Block
Block 0
Block 0
Block 1
Reserved
Unimplemented
Read ‘0’s
Block 1
Block 2
Unimplemented
Read ‘0’s
Reserved
Address
Range
000000h
0001FFh
000200h
001FFFh
002000h
002FFFh
003000h
003FFFh
004000h
005FFFh
006000h
007FFFh
008000h
Block Code Protection
Controlled By:
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
—
Unimplemented
Read ‘0’s
Unimplemented
Read ‘0’s
(Unimplemented Memory Space)
1FFFFFh
TABLE 20-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name
Bit 7
Bit 6
Bit 5
300008h CONFIG5L
—
—
—
300009h CONFIG5H CPD
CPB
—
30000Ah CONFIG6L
—
—
—
30000Bh CONFIG6H WRTD WRTB WRTC
30000Ch CONFIG7L
—
—
—
30000Dh CONFIG7H —
EBTRB
—
Legend: Shaded cells are unimplemented.
Note 1: Unimplemented, but reserved; maintain this bit set.
Bit 4
—
—
—
—
—
—
Bit 3
—⁽¹⁾
—
—⁽¹⁾
—
—⁽¹⁾
—
Bit 2
CP2
—
WRT2
—
EBTR2
—
Bit 1
CP1
—
WRT1
—
EBTR1
—
Bit 0
CP0
—
WRT0
—
EBTR0
—
 2002-2013 Microchip Technology Inc.
Preliminary
DS30485B-page 207