PIC18FXX39 Datasheet, PDF (83/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

9.0 I/O PORTS
Depending on the device selected, there are either
three or five ports available. Some pins of the I/O ports
are multiplexed with an alternate function from the
peripheral features on the device. In general, when a
peripheral is enabled, that pin may not be used as a
general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
• TRIS register (data direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (output latch)
The data latch (LAT register) is useful for read-modify-
write operations on the value that the I/O pins are
driving.
9.1 PORTA, TRISA and LATA
Registers
PORTA is a 7-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
High Impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch.
The Data Latch register (LATA) is also memory
mapped. Read-modify-write operations on the LATA
register reads and writes the latched output value for
PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The RA4/
T0CKI pin is a Schmitt Trigger input and an open drain
output. All other RA port pins have TTL input levels and
full CMOS output drivers.
The other PORTA pins are multiplexed with analog
inputs and the analog VREF+ and VREF- inputs. The
operation of each pin is selected by clearing/setting the
control bits in the ADCON1 register (A/D Control
Register1).
Note:
On a Power-on Reset, RA5 and RA3:RA0
are configured as analog inputs and read
as ‘0’. RA6 and RA4 are configured as
digital inputs.
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
PIC18FXX39
EXAMPLE 9-1: INITIALIZING PORTA
CLRF PORTA
CLRF LATA
MOVLW 0x07
MOVWF ADCON1
MOVLW 0xCF
MOVWF TRISA
; Initialize PORTA by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Configure A/D
; for digital inputs
; Value used to
; initialize data
; direction
; Set RA<3:0> as inputs
; RA<5:4> as outputs
FIGURE 9-1:
BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
RD LATA
Data
Bus
WR LATA
or
PORTA
D
Q
CK Q
Data Latch
D
Q
WR TRISA
CK Q
TRIS Latch
VDD
P
N
I/O pin⁽¹⁾
VSS
Analog
Input
Mode
RD TRISA
Q
D
TTL
Input
Buffer
EN
RD PORTA
SS Input (RA5 only)
To A/D Converter and LVD Modules
Note 1: I/O pins have protection diodes to VDD and VSS.
 2002-2013 Microchip Technology Inc.
Preliminary
DS30485B-page 83