PIC18FXX39 Datasheet, PDF (281/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

PIC18FXX39
TABLE 23-16: I²C BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
100
THIGH
Clock high time
100 kHz mode
400 kHz mode
101
TLOW
Clock low time
SSP Module
100 kHz mode
400 kHz mode
102 TR
SDA and SCL rise
time
SSP Module
100 kHz mode
400 kHz mode
103 TF
SDA and SCL fall
time
100 kHz mode
400 kHz mode
90
TSU:STA START condition
100 kHz mode
setup time
400 kHz mode
91
THD:STA START condition hold 100 kHz mode
time
400 kHz mode
106
THD:DAT Data input hold time 100 kHz mode
400 kHz mode
107
TSU:DAT Data input setup time 100 kHz mode
400 kHz mode
92
TSU:STO STOP condition
100 kHz mode
setup time
400 kHz mode
109 TAA
Output valid from
clock
100 kHz mode
400 kHz mode
110
TBUF
Bus free time
100 kHz mode
400 kHz mode
D102 CB
Bus capacitive loading
4.0
—
0.6
—
1.5 TCY
—
4.7
—
1.3
—
1.5 TCY
—
20 + 0.1 CB
—
1000
300
—
20 + 0.1 CB
4.7
0.6
4.0
0.6
0
0
250
100
4.7
0.6
—
—
4.7
1.3
1000
300
—
—
—
—
—
0.9
—
—
—
—
3500
—
—
—
—
400
s PIC18FXXX must operate at a
minimum of 1.5 MHz
s PIC18FXXX must operate at a
minimum of 10 MHz
s PIC18FXXX must operate at a
minimum of 1.5 MHz
s PIC18FXXX must operate at a
minimum of 10 MHz
ns
ns CB is specified to be from
10 to 400 pF
ns VDD  4.2V
ns VDD  4.2V
s Only relevant for Repeated
s ^{START condition}
s After this period, the first clock
s ^{pulse is generated}
ns
s
ns (Note 2)
ns
s
s
ns (Note 1)
ns
s Time the bus must be free
s ^{before a new transmission can}
start
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A Fast mode I²C bus device can be used in a Standard mode I²C bus system, but the requirement TSU:DAT  250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I²C bus specification) before the SCL line is
released.
 2002-2013 Microchip Technology Inc.
Preliminary
DS30485B-page 281