PIC18FXX39 Datasheet, PDF (285/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

PIC18FXX39
TABLE 23-21: A/D CONVERTER CHARACTERISTICS: PIC18FXX39 (INDUSTRIAL, EXTENDED)
PIC18LFXX39 (INDUSTRIAL)
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
A01 NR
Resolution
—
—
10
bit
A03 EIL
Integral linearity error
—
—
<±1
LSb VREF = VDD = 5.0V
A04 EDL
Differential linearity error
—
—
<±1
LSb VREF = VDD = 5.0V
A05 EG
Gain error
—
—
<±1
LSb VREF = VDD = 5.0V
A06 EOFF Offset error
—
—
<±1.5
LSb VREF = VDD = 5.0V
A10 _—
Monotonicity
guaranteed⁽²⁾
— VSS  VAIN  VREF
A20 VREF
A20A
Reference Voltage
(VREFH – VREFL)
1.8V
—
3V
—
—
V VDD < 3.0V
—
V VDD  3.0V
A21 VREFH Reference voltage High
AVSS
— AVDD + 0.3V V
A22 VREFL Reference voltage Low
AVSS – 0.3V —
VREFH
V
A25 VAIN Analog input voltage
AVSS – 0.3V — AVDD + 0.3V V VDD  2.5V (Note 3)
A30 ZAIN Recommended impedance of
—
—
2.5
k (Note 4)
analog voltage source
A50 IREF VREF input current (Note 1)
—
—
5
A During VAIN acquisition
—
—
150
A During A/D conversion cycle
Note 1: Vss  VAIN  VREF
2: The A/D conversion result never decreases with an increase in the Input Voltage, and has no missing codes.
3: For VDD < 2.5V, VAIN should be limited to < .5 VDD.
4: Maximum allowed impedance for analog voltage source is 10 k. This requires higher acquisition times.
FIGURE 23-22: A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
Q4
130
A/D CLK ¹³²
A/D DATA
9
8
7 ^{... ...} 2
1
0
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
NEW_DATA
TCY
DONE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
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Preliminary
DS30485B-page 285