PIC18FXX39 Datasheet, PDF (44/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

PIC18FXX39
TABLE 4-2: REGISTER FILE SUMMARY (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page:
TMR0H
TMR0L
T0CON
OSCCON^*
LVDCON
WDTCON
RCON
TMR1H
TMR1L
T1CON
TMR2^*
PR2^*
T2CON^*
SSPBUF
SSPADD
Timer0 Register High Byte
0000 0000 27, 101
Timer0 Register Low Byte
xxxx xxxx 27, 101
TMR0ON T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0 1111 1111 27, 99
—
—
—
—
—
—
—
*
---- ---0 27
—
—
IRVST
LVDEN
LVDL3
LVDL2
LVDL1
LVDL0 --00 0101 27, 191
—
—
—
—
—
—
—
SWDTE ---- ---0 27, 203
IPEN
—
—
RI
TO
PD
POR
BOR 0--1 11qq 25, 50, 80
Timer1 Register High Byte
xxxx xxxx 27, 103
Timer1 Register Low Byte
xxxx xxxx 27, 103
RD16
—
T1CKPS1 T1CKPS0
—
T1SYNC TMR1CS TMR1ON 0-00 0000 27, 103
*
*
*
*
*
*
*
*
0000 0000 27
*
*
*
*
*
*
*
*
1111 1111 27
*
*
*
*
*
*
*
*
-000 0000 27
SSP Receive Buffer/Transmit Register
SSP Address Register in I²C Slave mode. SSP Baud Rate Reload Register in I²C Master mode.
xxxx xxxx 27, 125
0000 0000 27, 134
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
SMP
CKE
D/A
WCOL SSPOV SSPEN
GCEN ACKSTAT ACKDT
A/D Result Register High Byte
A/D Result Register Low Byte
P
CKP
ACKEN
S
SSPM3
RCEN
R/W
SSPM2
PEN
UA
SSPM1
RSEN
BF
SSPM0
SEN
0000 0000 27, 126
0000 0000 27, 127
0000 0000 27, 137
xxxx xxxx 187,188
xxxx xxxx 187,188
ADCON0
ADCS1 ADCS0
CHS2
CHS1
CHS0 GO/DONE
—
ADON 0000 00-0 28, 181
ADCON1
ADFM
ADCS2
—
—
PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 28, 182
CCPR1H PWM Register1 High Byte (Read only)
xxxx xxxx 28, 124
CCPR1L^*
*
*
*
*
*
*
*
*
xxxx xxxx 28, 124
CCP1CON^*
—
—
*
*
*
*
*
*
--00 0000 28, 124
CCPR2H PWM Register2 High Byte (Read only)
xxxx xxxx 28, 124
CCPR2L^*
*
*
*
*
*
*
*
*
xxxx xxxx 28, 124
CCP2CON^*
—
—
*
*
*
*
*
*
--00 0000 28, 124
TMR3H
Timer3 Register High Byte
xxxx xxxx 28, 109
TMR3L
Timer3 Register Low Byte
xxxx xxxx 28, 109
T3CON
RD16
—
T3CKPS1 T3CKPS0
—
T3SYNC TMR3CS TMR3ON 0000 0000 28, 109
SPBRG
USART1 Baud Rate Generator
0000 0000 28, 168
RCREG
USART1 Receive Register
0000 0000 28, 175,
178
TXREG
USART1 Transmit Register
0000 0000 28, 173,
176
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D 0000 -010 28, 166
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x 28, 167
EEADR
Data EEPROM Address Register
0000 0000 28, 61,
65
EEDATA
Data EEPROM Data Register
0000 0000 28, 65
EECON2 Data EEPROM Control Register 2 (not a physical register)
---- ---- 28, 61,
65
EECON1
EEPGD
CFGS
—
FREE
WRERR WREN
WR
RD xx-0 x000 28, 62
Legend:
*
Note 1:
2:
3:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
These registers (or individual bits) are retained to maintain compatibility with PIC18FXX2 devices; however, the indicated bits are
reserved in PIC18FXX39 devices. Users should not alter the values of these bits. See Section 4.9.2 for details.
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator modes.
Bit 21 of the TBLPTRU allows access to the device configuration bits.
These registers and bits are reserved on the PIC18F2X39 devices; always maintain these clear.
DS30485B-page 44
Preliminary
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