PIC18FXX39 Datasheet, PDF (152/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

PIC18FXX39
16.4.7.1 Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated START/STOP condition,
de-asserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the baud rate
generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is
sampled high, the baud rate generator is reloaded with
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count, in the event that the clock
is held low by an external device (Figure 16-18).
FIGURE 16-18: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
SCL
BRG
Value
BRG
Reload
DX
DX-1
SCL de-asserted but slave holds
SCL low (clock arbitration)
SCL allowed to transition high
BRG decrements on
Q2 and Q4 cycles
03h
02h
01h
00h (hold off)
SCL is sampled high, reload takes
place and BRG starts its count
03h
02h
DS30485B-page 152
Preliminary
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