PIC18FXX39 Datasheet, PDF (124/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

PIC18FXX39
15.1.2 PWM DUTY CYCLE
The PWM duty cycle is set by the Motor Control module
when it writes a 10-bit value to the CCPR1L and
CCP1CON registers, where CCPR1L contains the
eight Most Significant bits and CCP1CON<5:4> con-
tains the two Least Significant bits. The duty cycle time
is given by the equation:
PWM duty cycle = (10-bit CCP register value) •
TOSC • (TMR2 prescale value)
where TOSC and the duty cycle are in the same unit of
time.
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This buffer-
ing is essential for glitchless PWM operation. At the
same time, the value of TMR2 is concatenated with
either an internal 2-bit Q clock, or 2 bits of the TMR2
prescaler. When the CCPR1H:latch pair value matches
that of the TMR2:latch pair, the PWM1 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
PWM Resolution (max)
=
log


F--F--P^-O--W^{--S---CM---}
-------l--o---g----_--2----_-------bits
where FPWM is the PWM frequency, or (1/PWM period).
Note:
If the PWM duty cycle value is longer than
the PWM period, the PWM1 pin will not be
cleared.
TABLE 15-1: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
All Other
RESETS
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1
PSPIF⁽¹⁾ ADIF
RCIF
TXIF
SSPIF
—
TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
PSPIE⁽¹⁾ ADIE
RCIE
TXIE
SSPIE
—
TMR2IE TMR1IE 0000 0000 0000 0000
IPR1
TMR2^*
PR2^*
T2CON^*
CCPR1L^*
PSPIP⁽¹⁾
*
*
*
*
ADIP
*
*
*
*
RCIP
*
*
*
*
TXIP
*
*
*
*
SSPIP
*
*
*
*
—
TMR2IP TMR1IP 0000 0000 0000 0000
*
*
*
0000 0000 0000 0000
*
*
*
1111 1111 1111 1111
*
*
*
-000 0000 -000 0000
*
*
*
xxxx xxxx uuuu uuuu
CCPR1H PWM Register1 (MSB) (read-only)
xxxx xxxx uuuu uuuu
CCP1CON^*
—
—
*
*
*
*
*
*
--00 0000 --00 0000
CCPR2L^*
*
*
*
*
*
*
*
*
xxxx xxxx uuuu uuuu
CCPR2H^* PWM Register2 (MSB) (read-only)
xxxx xxxx uuuu uuuu
CCP2CON^*
—
—
*
*
*
*
*
*
--00 0000 --00 0000
Legend:
*
Note 1:
x = unknown, u = unchanged, - = unimplemented, read as '0' unless otherwise noted. Shaded cells are not used by PWM
and Timer2.
These registers are retained to maintain compatibility with PIC18FXX2 devices; however, the indicated bits are reserved in
PIC18FXX39 devices. Users should not alter the values of these bits.
The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits clear.
DS30485B-page 124
Preliminary
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