PIC18FXX39 Datasheet, PDF (62/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

PIC18FXX39
REGISTER 6-1:
EECON1 REGISTER (ADDRESS FA6h)
R/W-x R/W-x
U-0
R/W-0
EEPGD CFGS
—
FREE
bit 7
R/W-x
WRERR
R/W-0
WREN
R/S-0
WR
R/S-0
RD
bit 0
bit 7
EEPGD: FLASH Program or Data EEPROM Memory Select bit
1 = Access FLASH program memory
0 = Access data EEPROM memory
bit 6
CFGS: FLASH Program/Data EE or Configuration Select bit
1 = Access configuration or calibration registers
0 = Access FLASH program or data EEPROM memory
bit 5
Unimplemented: Read as '0'
bit 4
FREE: FLASH Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0 = Perform write only
bit 3
WRERR: FLASH Program/Data EE Error Flag bit
1 = A write operation is prematurely terminated
(any MCLR or any WDT Reset during self-timed programming in normal operation)
0 = The write operation completed
Note: When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows tracing
of the error condition.
bit 2
WREN: FLASH Program/Data EE Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM
bit 1
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)
0 = Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1 = Initiates an EEPROM read
(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)
in software. RD bit cannot be set when EEPGD = 1.)
0 = Does not initiate an EEPROM read
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS30485B-page 62
Preliminary
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