PIC18FXX39 Datasheet, PDF (28/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

PIC18FXX39
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
ADRESH 2439 4439 2539 4539
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADRESL
2439 4439 2539 4539
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0 2439 4439 2539 4539
0000 00-0
0000 00-0
uuuu uu-u
ADCON1 2439 4439 2539 4539
00-- 0000
00-- 0000
uu-- uuuu
CCPR1H
CCPR1L^*
CCP1CON^*
2439 4439 2539 4539
2439 4439 2539 4539
2439 4439 2539 4539
xxxx xxxx
xxxx xxxx
--00 0000
uuuu uuuu
uuuu uuuu
--00 0000
uuuu uuuu
uuuu uuuu
--uu uuuu
CCPR2H
CCPR2L^*
CCP2CON^*
2439 4439 2539 4539
2439 4439 2539 4539
2439 4439 2539 4539
xxxx xxxx
xxxx xxxx
--00 0000
uuuu uuuu
uuuu uuuu
--00 0000
uuuu uuuu
uuuu uuuu
--uu uuuu
TMR3H
2439 4439 2539 4539
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR3L
2439 4439 2539 4539
xxxx xxxx
uuuu uuuu
uuuu uuuu
T3CON
2439 4439 2539 4539
0000 0000
uuuu uuuu
uuuu uuuu
SPBRG
2439 4439 2539 4539
0000 0000
0000 0000
uuuu uuuu
RCREG
2439 4439 2539 4539
0000 0000
0000 0000
uuuu uuuu
TXREG
2439 4439 2539 4539
0000 0000
0000 0000
uuuu uuuu
TXSTA
2439 4439 2539 4539
0000 -010
0000 -010
uuuu -uuu
RCSTA
2439 4439 2539 4539
0000 000x
0000 000x
uuuu uuuu
EEADR
2439 4439 2539 4539
0000 0000
0000 0000
uuuu uuuu
EEDATA
2439 4439 2539 4539
0000 0000
0000 0000
uuuu uuuu
EECON1 2439 4439 2539 4539
xx-0 x000
uu-0 u000
uu-0 u000
EECON2 2439 4439 2539 4539
---- ----
---- ----
---- ----
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
* These registers are retained to maintain compatibility with PIC18FXX2 devices; however, one or more bits
are reserved. Users should not modify the value of these bits. See Section 4.9.2 for details.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
Oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
DS30485B-page 28
Preliminary
 2002-2013 Microchip Technology Inc.