PIC18FXX39 Datasheet, PDF (80/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

PIC18FXX39
8.5 RCON Register
The RCON register contains the bit which is used to
enable prioritized interrupts (IPEN). For PIC18FXX39
devices, the IPEN bit must always be set (= 1) for the
ProMPT kernel to function correctly. Refer to page 69
for a more detailed discussion on interrupt priorities.
REGISTER 8-10: RCON REGISTER
R/W-0
U-0
IPEN⁽¹⁾
—
bit 7
U-0
R/W-1
R-1
—
RI
TO
bit 7
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
IPEN⁽¹⁾: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (not used)
Unimplemented: Read as '0'
RI: RESET Instruction Flag bit
For details of bit operation, see Register 4-3
TO: Watchdog Time-out Flag bit
For details of bit operation, see Register 4-3
PD: Power-down Detection Flag bit
For details of bit operation, see Register 4-3
POR: Power-on Reset Status bit
For details of bit operation, see Register 4-3
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-3
Note 1: Maintain this bit set (= 1).
R-1
R/W-0 R/W-0
PD
POR
BOR
bit 0
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS30485B-page 80
Preliminary
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