PIC18FXX39 Datasheet, PDF (73/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

PIC18FXX39
REGISTER 8-3: INTCON3 REGISTER
R/W-1 R/W-1
U-0
R/W-0 R/W-0
U-0
R/W-0 R/W-0
INT2IP⁽¹⁾ INT1IP⁽¹⁾
—
INT2IE INT1IE
—
INT2IF INT1IF
bit 7
bit 0
bit 7
INT2IP⁽¹⁾: INT2 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
INT1IP⁽¹⁾: INT1 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
Unimplemented: Read as '0'
bit 4
INT2IE: INT2 External Interrupt Enable bit
1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt
bit 3
INT1IE: INT1 External Interrupt Enable bit
1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt
bit 2
Unimplemented: Read as '0'
bit 1
INT2IF: INT2 External Interrupt Flag bit
1 = The INT2 external interrupt occurred (must be cleared in software)
0 = The INT2 external interrupt did not occur
bit 0
INT1IF: INT1 External Interrupt Flag bit
1 = The INT1 external interrupt occurred (must be cleared in software)
0 = The INT1 external interrupt did not occur
Note 1: Maintain this bit cleared (= 0).
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
 2002-2013 Microchip Technology Inc.
Preliminary
DS30485B-page 73