PIC18FXX39 Datasheet, PDF (227/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

PIC18FXX39
CLRF
Clear f
Syntax:
Operands:
Operation:
[ label ] CLRF f [,a]
0  f  255
a [0,1]
000h  f
1Z
Status Affected: Z
Encoding:
0110 101a ffff ffff
Description:
Clears the contents of the specified
register. If ‘a’ is 0, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will
be selected as per the BSR value
(default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write
register 'f'
Example:
CLRF
Before Instruction
FLAG_REG =
After Instruction
FLAG_REG =
FLAG_REG,1
0x5A
0x00
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CLRWDT
Operands:
None
Operation:
000h  WDT,
000h  WDT postscaler,
1  TO,
1  PD
Status Affected: TO, PD
Encoding:
0000 0000 0000 0100
Description:
CLRWDT instruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits
TO and PD are set.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
No
operation
Q3
Process
Data
Q4
No
operation
Example:
CLRWDT
Before Instruction
WDT Counter
=
After Instruction
WDT Counter
=
WDT Postscaler =
TO
=
PD
=
?
0x00
0
1
1
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Preliminary
DS30485B-page 227