PIC18FXX39 Datasheet, PDF (89/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

PIC18FXX39
9.3 PORTC, TRISC and LATC
Registers
PORTC is a 6-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a High Impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register reads and writes the latched output value for
PORTC.
PORTC is multiplexed with the serial communication
functions (Table 9-5). PORTC pins have Schmitt
Trigger input buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the corre-
sponding peripheral section for the correct TRIS bit
settings.
Note: On a Power-on Reset, these pins are
configured as digital inputs.
The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write of the TRIS register,
without concern due to peripheral overrides.
EXAMPLE 9-3: INITIALIZING PORTC
CLRF PORTC
CLRF LATC
MOVLW 0xC9
MOVWF TRISC
; Initialize PORTC by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RC<3>,RC<0> as inputs,
; RC<5:4> as outputs, and
; RC<7:6> as inputs
PIC18FXX39 devices differ from other PIC18 micro-
controllers in allocation of PORTC pins. For most
PIC18 devices, PORTC is an 8-bit-wide port. For the
PIC18FXX39 family, two of the PORTC pins (RC1 and
RC2) are re-allocated as PWM output only pins for use
with the Motor Control kernel. To maintain pinout com-
patibility with other PIC^® devices, the remaining
PORTC pins are assigned in a manner consistent with
other PIC18 devices. For this reason, PORTC has pins
RC0 and RC3 through RC7, but not RC1 and RC2.
To maintain compatibility with PIC18FXX2 devices, the
individual port and corresponding latch and direction
bits for RC1 and RC2 are present in the appropriate
registers, but are not available to the user. To avoid
erratic device operation, the values of these bits should
not be modified.
FIGURE 9-7:
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
Port/Peripheral Select⁽²⁾
VDD
Peripheral Data Out
RD LATC
Data Latch
0
Data Bus
WR LATC or
DQ
P
WR PORTC
CK Q
1
TRIS Latch
DQ
WR TRISC
CK Q
N
RD TRISC
Peripheral Output
Enable⁽³⁾
RD PORTC
Peripheral Data In
VSS
QD
EN
Note 1:
2:
3:
I/O pins have diode protection to VDD and VSS.
Port/Peripheral Select signal selects between port data (input) and peripheral output.
Peripheral Output Enable is only active if Peripheral Select is active.
I/O pin⁽¹⁾
Schmitt
Trigger
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Preliminary
DS30485B-page 89