PIC18FXX39 Datasheet, PDF (306/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

PIC18FXX39
APPENDIX C: CONVERSION
CONSIDERATIONS
The considerations for converting applications from
previous versions of PIC18 microcontrollers (i.e.,
PIC18FXX2 devices) are listed in Table C-1.
A specific list of resources that are unavailable to
PIC18FXX2 applications in PIC18FXX39 devices is
presented in Table C-2.
TABLE C-1: CONVERSION CONSIDERATIONS BETWEEN PIC18FXX2 AND PIC18FXX39 DEVICES
Characteristic
Pins
Available Packages
Voltage Range
Frequency Range
Available Program Memory (bytes)
Available Data RAM (bytes)
Data EEPROM
Interrupt Sources
Interrupt Priority Levels
Timers (available to users)
Timer1 Oscillator option
Oscillator Switching
Capture/Compare/PWM
Motor Control Kernel
A/D
Communications
Code Protection
PIC18FXX2
28/40/44
DIP, PDIP, SOIC, PLCC, QFN, TQFP
2.0 - 5.5V
DC - 40 MHz
16K or 32K
768 or 1536
256
17 or 18
Two levels:
low priority (vector at 0008h)
high priority (vector at 0018h)
4
yes
yes
2 CCP
no
10-bit, 5 or 8 channels,
7 conversion clock selects
PSP, AUSART, MSSP (SPI and I²C)
By 8K block with separate 512-byte
boot block; protection from external
reads and writes, Table Read and
intra-block Table Read
PIC18FXX39
28/40/44
DIP, PDIP, SOIC, QFN, TQFP
2.0 - 5.5V
4 - 40 MHz (20 MHz optimal)
12K or 24K
640 or 1408
256
15 or 16
One level when using Motor Control:
vector at 0008h
3
no
no
2 PWM only, available only through
Motor Control kernel
yes
10-bit, 5 or 8 channels,
7 conversion clock selects
PSP, AUSART, MSSP (SPI and I²C)
By 8K block with separate 512-byte
boot block; protection from external
reads and writes, Table Read and intra-
block Table Read; Block 3 not protected
on PIC18FX539
TABLE C-2: UNAVAILABLE RESOURCES (COMPARED TO PIC18FXX2)
Resource Type
I/O Resources
Registers
SFR bits
Interrupts and
Interrupt Resources
Timer Resources
CCP Resources
Configuration Word bits
Item(s)
RC1; RC2; T1OSO; T1OSI
CCP1CON; CCP2CON; CCPR1L; CCPR2L; TMR2; PR2; T2CON; OSCCON
CCP1IE; CCP1IF; CCP1IP; CCP21E; CCP21F; CCP2IP; T1OSCEN; T3CCP1; TMR2ON;
TOUTPS<3:0>; T2CKPS<1:0>; T3CCP2; SFS; RC1; RC2; TRISC1; TRISC2; LATC1; LATC2
CCP1 Capture/Compare match; CCP2 Capture/Compare match; High priority interrupts
(when Motor Control is used; reserved for Timer2)
Timer2 (available only through the Motor Control kernel); Timer2 as a clock source for
MSSP module (SPI mode)
Capture and Compare functionality; Timer1 reset on special event; Timer3 reset on special
event; A/D conversion on special event; Interrupt on special event
OSCEN; CCP2MX; CP3; WRT3; EBTR3
DS30485B-page 306
Preliminary
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