MRF24XA_15 Datasheet, PDF (82/258 Pages) Microchip Technology – Low-Power, 2.4 GHz ISM-Band IEEE 802.15.4™ RF

MRF24XA
REGISTER 3-12: PIR4 (PERIPHERAL INTERRUPT REGISTER 4)
ADDRESS: 0x07
R/W/HS/HC-0 R/W/HS/HC-0 R/W/HS/HC-0 R/W/HS/HC-0 R/W/HS/HC-0 R/W/HS/HC-0 R/W/HS/HC-0 R/W/HS/HC-0
TXSFDIF
RXSFDIF
ERRORIF
WARNIF
EDCCAIF
GPIO2IF
GPIO1IF
GPIO0IF
bit 7
bit 0
Legend: R = Readable bit W = Writable bit
-n = Value at POR
‘1’ = Bit is set
r = Reserved
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-3
bit 2
bit 1
bit 0
Out of scope
GPIO2IF: GPIO2 Interrupt Flag bit
Set by the device if the GPIOMODE register is set to normal operation, the GPIO is enabled and
configured to input and the level matches with the polarity.
GPIO1IF: GPIO1 Interrupt Flag bit
Set by the device if the GPIOMODE register is set to normal operation, the GPIO is enabled and
configured to input and the level matches with the polarity.
GPIO0IF: GPIO0 Interrupt Flag bit
Set by the device if the GPIOMODE register is set to normal operation, the GPIO is enabled and
configured to input and the level matches with the polarity.
REGISTER 3-13: PIE4 (PERIPHERAL INTERRUPT ENABLE 4)
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
R/W-0
TXSFDIE
RXSFDIE ERRORIE
WARNIE
EDCCAIE
GPIO2IE
bit 7
ADDRESS: 0x0B
R/W-0
R/W-0
GPIO1IE
GPIO0IE
bit 0
Legend: R = Readable bit W = Writable bit
-n = Value at POR
‘1’ = Bit is set
r = Reserved
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-3
bit 2
bit 1
bit 0
Out of scope
GPIO2IE: GPIO2 Interrupt Enable bit
This bit masks the GPIO2IF interrupt register.
GPIO1IE: GPIO1 Interrupt Enable bit
This bit masks the GPIO1IF interrupt register.
GPIO0IE: GPIO0 Interrupt Enable bit
This bit masks the GPIO0IF interrupt register.
DS70005023C-page 82
Preliminary
 2015 Microchip Technology Inc.