MRF24XA_15 Datasheet, PDF (19/258 Pages) Microchip Technology – Low-Power, 2.4 GHz ISM-Band IEEE 802.15.4™ RF

MRF24XA
REGISTER 2-2: STATUS (DEVICE STATUS)
R/HS
R/HS
R/HS
R/W/HC-0
INITDONESF
bit 7
XTALSF
REGSF
CALST
R/W-0
XTALDIS
R/W-0
DSLEEP
Address: 0x03
R/HS
R/W/HC
IDLESF
POR
bit 0
Legend: R = Readable bit
-n = Value at POR
r = Reserved
W = Writable bit
‘1’ = Bit is set
HC = Hardware Clear
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
HS = Hardware Set
bit 7
INITDONESF: Device Initialization Status Flag bit
Indicates that the ready state is reached since the LDO is on, (If VREGIF = 1). INITDONESF is
asserted when RDYIF is set for the first time after VREGIF. This bit is only cleared on reset (POR,
DEVFRST and PINRST).
bit 6
XTALSF: Crystal Status Flag bit
XTALSF = 1, indicates that 16 MHz system clock (from the crystal oscillator) is active. This bit is
cleared either when XTALDIS is set or reset (POR, DEVFRST, PINRST).
XTALSF = 0, indicates that the crystal oscillator is either powered off (XTALDIS = 1) or is ramping up
or is not stabilized yet, and the system clock is inactive.
bit 5
REGSF: Configuration Registers Status Flag bit
REGSF = 1 indicates that all the 1.2V register content is valid. Either it holds the default value after
reset and the retention memory does not hold any data to restore, or the register configura-
tions are restored from the retention memory.
REGSF = 0 indicates that registers from 0x08-0x6E are invalid. This occurs when the wake-up proce-
dure from Deep Sleep mode did not complete the register restore operation yet. This bit is
only cleared on Reset (POR, DEVFRST, and PINRST).
bit 4
CALST: Calibration Start bit
MCU sets this bit to start Calibration procedure after a CALSOIF or CALHAIF interrupt occurred. MCU
may not clear it to abort Calibration. The device clears CALST when the Calibration is completed
(CALHAIF = 0 indicates success, CALHAIF = 1 indicates failure). Issuing CALST operation without
CALHAIF/CALSOIF terminates without any effect on the device.
bit 3
XTALDIS: Crystal Disable bit
MCU sets this bit to send the device into XTAL OFF state (reachable from ready state). XTALSF auto-
matically gets cleared. The SPI register access is performed when crystal is not working.
bit 2
DSLEEP: Deep-Sleep bit
MCU sets this bit to send the device into Deep Sleep state. Following DSLEEP = 1 , the SPI access
to the SFR is shut off, and the SPI pins must be quite, unless the host MCU wants to wake-up the
device. When DSLEEP is set, the device transitions through register backup (taking cca. 16 ìs) before
LDO is powered off.
bit 1
IDLESF: Idle Status Flag bit
Indicates Idle state of the device when all of the following bits are deasserted:
• TXBUFEMPTY = 0 since it is transmitted (TXST)
• Network layer security finished (TXENC)
• Crypto engine finished (RXDEC)
• Energy detect operation finished (EDST)
• Clear Channel Assessment finished (CCAST)
bit 0
POR: Power-on-Reset Flag bit
The 3.3V POR flag status. The device sets this only on 3.3V power-up (e.g., when battery is
changed). Cleared by host MCU to be able to sense a Brown-out Reset (BOR). Settable for software
testing.
 2015 Microchip Technology Inc.
Preliminary
DS70005023C-page 19