MRF24XA_15 Datasheet, PDF (11/258 Pages) Microchip Technology – Low-Power, 2.4 GHz ISM-Band IEEE 802.15.4™ RF

2.4.3 RESET (RESET) PIN
An external Hardware Reset is performed by asserting
the RESET pin 18 low. If the RESET pin is deasserted,
MRF24XA starts the internal Calibration process. RDYIF
interrupt is set when the device is ready to use. The
RESET pin contains an internal weak pull-up resistor.
2.4.4
INTERRUPT (INT) PIN
The Interrupt (INT) pin 13 provides an interrupt signal
to the host MCU from MRF24XA where the signal is
active-low polarity. Interrupt sources must be enabled
and unmasked before the INT pin becomes active.
Refer to Section 3.2 “Interrupts” for the functional
description of interrupts.
2.4.5
GENERAL PURPOSE INPUT/
OUTPUT (GPIO) PINS
Three GPIO pins are configured individually for control or
monitoring purposes. The TRISGPIOx bits in the GPIO
register (0x0D) configures the input or output selection.
GPIO data is read or written through the GPIO bits of
GPIO register. The GPIO interrupt polarity is selected
through GPIOxP bits in the STGPIO (0x0E) register.
GPIO lines in Input mode are used in Schmitt Trigger
Input mode. STENGPIOx bits of STGPIO register
enables Schmitt Triggers. GPIOs are also used to
monitor the internal blocks. The GPIOMODE bits <3:0>
of the PINCON (0x0C) register selects these
monitoring functions.
MRF24XA
2.4.6
SERIAL PERIPHERAL INTERFACE
(SPI) PORT PINS
MRF24XA communicates with a host MCU through a
4-wire SPI port as a slave device. MRF24XA supports
SPI mode 0,0, which requires that SCK idles in a low
state. The CS pin must be held low while communicat-
ing with MRF24XA. Figure 2-3 illustrates timing for a
read and a write operation. MRF24XA receives the
data through the SDI pin and clocks in on the rising
edge of SCK. MRF24XA sends data through the SDO
pin and clocks out on the falling edge of SCK. The SDO
lines preserve its HiZ state in Deep Sleep mode.
 2015 Microchip Technology Inc.
Preliminary
DS70005023C-page 11