MRF24XA_15 Datasheet, PDF (13/258 Pages) Microchip Technology – Low-Power, 2.4 GHz ISM-Band IEEE 802.15.4™ RF

MRF24XA
2.6 Memory Organization
Table 2-5 shows that memory is functionally divided
into Special Function Registers (SFR) and data buffers.
The SFRs provide control, status and device Configura-
tion addressing for MRF24XA operations. Data buffers
serve as temporary buffers for data transmission and
reception. Memory is accessed through two addressing
methods: Short (1 byte) and Long (2 bytes).
2.6.1 ADDRESS OVERVIEW
MRF24XA contains two Addressing modes:
• Short Address Mode: Requires one byte for
address, and may be used to access the first 64
on-chip control registers.
• Long Address Mode: Requires two bytes for
address, and may be used to access all on-chip
registers and data buffers. Figure 2-4 illustrates
these modes.
TABLE 2-5: MRF24XA MEMORY MAP
0x00
...
0x0F
0x10
...
0x2F
0x30
...
0x39
0x3A
...
0x3F
0x40
SYSTEM LEVEL
MAC
PHY
TX and EXTDEV
PIR4 (0x07)
PIE1 (0x08)
...
MAC
0x60
...
PHY
0x70
0x1FF
0x200
...
0x284
0x285
...
0x2FF
0x300
...
0x384
0x385
...
0x3FF
RESERVED
DATA BUFFER 1
RESERVED
DATA BUFFER 2
RESERVED
 2015 Microchip Technology Inc.
Preliminary
DS70005023C-page 13