MRF24XA_15 Datasheet, PDF (103/258 Pages) Microchip Technology – Low-Power, 2.4 GHz ISM-Band IEEE 802.15.4™ RF

MRF24XA
REGISTER 4-2: RATECON (RATE CONFIGURATION REGISTER)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DIS2000
DIS1000
DIS500
DIS250
DISSTD
DIS125
bit 7
ADDRESS: 0x36
R/W-1
R/W-1
OPTIMAL
PSAV
bit 0
Legend: R = Readable bit W = Writable bit
-n = Value at POR
‘1’ = Bit is set
r = Reserved
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
DIS2000: Disable 2 Mbps Frame Reception bit
If this bit is set, then reception of 2 Mbps frames is disabled.
bit 6
DIS1000: Disable 1 Mbps Frame Reception bit
If this bit is set, then reception of 1 Mbps frames is disabled.
bit 5
DIS500: Disable 500 kbps Frame Reception bit
If this bit is set, then reception of 500 kbps frames is disabled.
bit 4
DIS250: Disable 250 kbps Frame Reception bit
If this bit is set, then reception of 250 kbps frames with non-standard-compliant SFD patterns is
disabled.
bit 3
DISSTD: Disable IEEE 802.15.4 compliant Frame Reception bit
If this bit is set, then reception of 250 kbps frames with IEEE 802.15.4 compliant SFD patterns is
disabled.
bit 2
DIS125: Disable 125 kbps Frame Reception bit
If this bit is set, then reception of 125 kbps frames is disabled.
bit 1
OPTIMAL: Optimized Preamble Selection bit
When this bit is set, then optimized preamble is used instead of legacy.
1 = Optimized preamble
0 = Legacy preamble
bit 0
PSAV: Power-Save Mode Selection bit
When this bit is set, frame detection is dependent on the RSSI signal, and the receive signal processor
is turned on when a sudden and significant increase (PSAVTHR<3:0>) is detected in the signal strength
or the signal strength is above an absolute level (DESENSTHR<3:0>).
1 = Power-Save mode
0 = Hi-Sensitivity mode
 2015 Microchip Technology Inc.
Preliminary
DS70005023C-page 103