MRF24XA_15 Datasheet, PDF (80/258 Pages) Microchip Technology – Low-Power, 2.4 GHz ISM-Band IEEE 802.15.4™ RF

MRF24XA
REGISTER 3-11: PIR4 (PERIPHERAL INTERRUPT REGISTER 4)
ADDRESS: 0x07
R/W/HS/HC-0 R/W/HS/HC-0 R/W/HS/HC-0 R/W/HS/HC-0 R/W/HS/HC-0 R/W/HS/HC-0 R/W/HS/HC-0 R/W/HS/HC-0
TXSFDIF
RXSFDIF
ERRORIF
WARNIF
EDCCAIF
GPIO2IF
GPIO1IF
GPIO0IF
bit 7
bit 0
Legend: R = Readable bit W = Writable bit
-n = Value at POR
‘1’ = Bit is set
r = Reserved
HC = Hardware Clear
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
HS = Hardware Set
bit 7
TXSFDIF: Transmit SFD Sent Interrupt Flag bit
Set by the device when the last sample of the SFD field is sent into the air.
Nonpersistent, cleared by SPI read.
bit 6
RXSFDIF: Receive SFD Detected Interrupt Flag bit
Set by the device when the SFD field of the received frame is detected⁽¹⁾.
Nonpersistent, cleared by SPI read.
bit 5
ERRORIF: General Error Interrupt Flag bit
Set by the device, when malfunction state is reached.
bit 4
WARNIF: Warning Interrupt Flag bit
Set by the device when one of the following is occurred:
• Battery voltage drops below the threshold by BATMON<4:0> at 0x3F
• Indicating that resistor is missing or not connected well
bit 3
EDCCAIF: Energy Detect/CCA Done Interrupt Flag bit
Set by the device when Energy-detect or CCA measurement is complete (following that the host MCU
sets the EDST/CCAST bit to start the measurement and the device is clearing it in on completion).
Nonpersistent. Cleared by SPI read.
bit 2
GPIO2IF: GPIO2 Interrupt Flag bit
Set by the device if the GPIOMODE register is set to normal operation, the GPIO is enabled and
configured to input and the level matches with the polarity.
bit 1
GPIO1IF: GPIO1 Interrupt Flag bit
Set by the device if the GPIOMODE register is set to normal operation, the GPIO is enabled and
configured to input and the level matches with the polarity.
bit 0
GPIO0IF: GPIO0 Interrupt Flag bit
Set by the device if the GPIOMODE register is set to normal operation, the GPIO is enabled and
configured to input and the level matches with the polarity.
Note 1: The detection latency (0…1 µs after the last sample of the SFD). Note that the SFD may trigger on noise
or interference. Note that the CFOMEAS<7:0> indication becomes valid when RXSFDIF is asserted.
TABLE 3-2: REGISTERS ASSOCIATED WITH INTERRUPTS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PIR1
PIR2
PIR3
PIR4
PIE1
PIE2
PIE3
PIE4
PINCON
Legend:
VREGIF
TXIF
RXIF
TXSFDIF
r
TXIE
RXIE
TXSFDIE
r
r = Reserved.
r
TXENCIF
RXDECIF
RXSFDIF
TXENCIE
RXDECIE
RXSFDIE
GIE
RDYIF
TXMAIF
RXTAGIF
ERRORIF
RDYIE
TXMAIE
RXTAGIE
ERRORIE
r
IDLEIF
TXACKIF
r
WARNIF
IDLEIE
TXACKIE
r
WARNIE
IRQIF
r
TXCSMAIF
RXIDENTIF
EDCCAIF
r
TXCSMAIE
RXIDENTIE
EDCCAIE
Bit 2
Bit 1
CALSOIF
CALHAIF
TXSZIF
TXOVFIF
RXFLTIF
RXOVFIF
GPIO2IF
GPIO1IF
CALSOIE
CALHAIE
TXSZIE
TXOVFIE
RXFLTIE
RXOVFIE
GPIO2IE
GPIO1IE
GPIOMODE<3:0>
Bit 0
r
FRMIF
STRMIF
GPIO0IF
r
FRMIE
STRMIE
GPIO0IE
DS70005023C-page 80
Preliminary
 2015 Microchip Technology Inc.