MRF24XA_15 Datasheet, PDF (77/258 Pages) Microchip Technology – Low-Power, 2.4 GHz ISM-Band IEEE 802.15.4™ RF

MRF24XA
3.2.2
PIRX- PERIPHERAL INTERRUPT
REGISTERS
Register bits of PIR1 to PIR4 registers indicates the
source of the interrupt. The interrupt must be enabled
when the appropriate bit is set to ‘1’ in the correspond-
ing PIEx register. MRF24XA automatically clears the
contents of the PIRX registers when the host MCU
reads the content of the register. MCU must store the
PIRX register values in the firmware as needed .
REGISTER 3-8:
R/HS-1
VREGIF
bit 7
PIR1 (PERIPHERAL INTERRUPT REGISTER 1)
R-0
R/HS-0
R/W/HC-0
R-0
R/W/HS-0
r
RDYIF
IDLEIF
r
CALSOIF
ADDRESS: 0x04
R/W/HS-0
R-0
CALHAIF
r
bit 0
Legend: R = Readable bit W = Writable bit
-n = Value at POR
‘1’ = Bit is set
r = Reserved
HC = Hardware Clear
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
HS = Hardware Set
bit 7
VREGIF: Voltage regulator On Interrupt Flag bit⁽¹⁾
This is a nonpersistent bit. The register bit initializes to 1 on 1.2V reset except when RESET is used
and only cleared when PIR1 is read. Note that the corresponding IE bit is not implemented.
bit 6
Reserved: Maintain as ‘0’
bit 5
RDYIF: Ready state Interrupt Flag bit
Set each time when READY state is reached:
• When Calibration ended (CALST = 0)
• When initialization ended (INITDONESF = 1)
• When crystal is ramped up (XTALSF = 1)
This bit is cleared when PIR1 is read.
bit 4
IDLEIF: Idle state Interrupt Flag bit
Set each time the IDLESF is set and if MCU did not trigger this change. This is unchanged when MCU
aborts an action by clearing either of TXST, TXENC, RXDEC, EDST or CCA bits. This bit is cleared
when PIR1 is read.
bit 3
Reserved: Maintain as ‘0’
bit 2
CALSOIF: Calibration Soft Interrupt Flag bit
This flag indicates that maybe Calibration is needed (CALST) although the radio is still functional. It also
warns of a possible degradation in signal quality and current consumption, and a risk of CALHAIF inter-
rupt. This bit is cleared when PIR1 is read.
bit 1
CALHAIF: Calibration Hard Interrupt Flag bit
This flag indicates that immediate Calibration (CALST) is mandatory, otherwise the radio is not func-
tional. The device enters into malfunction state. This bit is cleared when PIR1 is read.
bit 0
Reserved: Maintain as ‘0’
Note 1: Generated non-maskable interrupt is gated off until the 1.2V reset is released.
 2015 Microchip Technology Inc.
Preliminary
DS70005023C-page 77