MRF24XA_15 Datasheet, PDF (73/258 Pages) Microchip Technology – Low-Power, 2.4 GHz ISM-Band IEEE 802.15.4™ RF

MRF24XA
3.2.1
PIEx - INTERRUPT ENABLE
REGISTERS
Register bits of PIE1 to PIE4 registers enable the
appropriate interrupt sources to generate interrupts to
the host MCU through INT pin. The interrupt is enabled
when the appropriate bit is set to ‘1’.
REGISTER 3-4:
R-0
r
bit 7
PIE1 (PERIPHERAL INTERRUPT ENABLE 1)
R/W-1
R/W-1
R-0
R/W-1
RDYIE
IDLEIE
r
CALSOIE
ADDRESS: 0x08
R/W-1
R-0
CALHAIE
r
bit 0
Legend: R = Readable bit W = Writable bit
-n = Value at POR
‘1’ = Bit is set
r = Reserved
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Reserved: Maintain as ‘0’
RDYIE: Ready Interrupt Enable bit
This bit masks the RDYIF interrupt bit.
IDLEIE: Idle Interrupt Enable bit
This bit masks the IDLEIF interrupt bit.
Reserved: Maintain as ‘0’
CALSOIE: Calibration Soft Interrupt Enable bit
This bit masks the CALSOIF interrupt bit.
CALHAIE: Calibration Hard Interrupt Enable bit
This bit masks the CALHAIF interrupt bit.
Reserved: Maintain as ‘0’
 2015 Microchip Technology Inc.
Preliminary
DS70005023C-page 73