MRF24XA_15 Datasheet, PDF (72/258 Pages) Microchip Technology – Low-Power, 2.4 GHz ISM-Band IEEE 802.15.4™ RF

MRF24XA
TABLE 3-1: REGISTERS ASSOCIATED WITH RESET
Name
Bit 7
Bit 6
Bit 5
Bit 4
REGRST
r
FSMRST
r
Legend: r = Reserved, read as ‘0’.
Bit 3
Bit 2
Bit 1
REGRST<5:0>
FSMRST<4:0>
Bit 0
3.2 Interrupts
MRF24XA has one interrupt (INT), pin 13 that signals
interrupt events to the host MCU. Interrupt sources are
enabled through PIE1 (0x08) to PIE4 (0x0B) register
bits. All interrupts are enabled or disabled using GIE bit
(PINCON<6>). If GIE bit is cleared, all interrupts are
disabled and INT pin remains in inactive state. Despite
having the interrupts cleared by GIE bit clearing, the
interrupt flags of the enabled interrupt sources are set.
Interrupt flags are located in the PIR1 (0x04) to PIR4
(0x07) registers. The PIRX register bits clears-to-zero
upon read.
Therefore, the host MCU must read and store the value
of the PIRX registers and check the bits to determine
which interrupt occurred. The INT pin continues to
signal an interrupt until all active interrupts flags in
PIRX registers are read.
REGISTER 3-3: PINCON (PIN CONFIGURATION REGISTER)
R-0
R/W-1
R-0
R-x
r
GIE
r
IRQIF
bit 7
ADDRESS: 0x0C
R/W-0000
GPIOMODE<3:0>
bit 0
Legend: R = Readable bit W = Writable bit
-n = Value at POR
‘1’ = Bit is set
r = Reserved
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3-0
Reserved: Maintain as ‘0’
GIE: General Interrupt Enable bit
This bit enables to output IRQIF on INT pin. Note that the polarity of INT pin is active-low.
Reserved: Maintain as ‘0’
IRQIF: Interrupt Request Pending bit
This bit is the OR relationship of the enabled interrupt flags.
GPIOMODE <3:0>: GPIO Mode Field bits
This bit field is out of scope.
DS70005023C-page 72
Preliminary
 2015 Microchip Technology Inc.