MRF24XA_15 Datasheet, PDF (203/258 Pages) Microchip Technology – Low-Power, 2.4 GHz ISM-Band IEEE 802.15.4™ RF

MRF24XA
REGISTER 9-5: RXCON1 (MAC RECEIVE CONTROL 1 REGISTER)
ADDRESS: 0x15
R/W/HC/HS-0 R/W-0
R/W/HC-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
RXEN
NOPA
RXDEC RSVLQIEN RSVRSSIEN RSVCHDREN RSVCFOEN
r
bit 7
bit 0
Legend: R = Readable bit W = Writable bit
-n = Value at POR
‘1’ = Bit is set
r = Reserved
HC = Hardware Clear
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
HS = Hardware Set
bit 7
bit 6-0
RXEN: Receive Enable bit^{(1, 2)}
This bit Enables/Disables the packet reception. If an RX packet is being received, clearing this bit
causes that packet to be discarded.
1 = RX enabled
0 = RX disabled
Hardware clear/set when:
• Cleared when TRXMODE is set to TX-Streaming mode
• Set when TRXMODE is set to RX-Streaming mode
Clearing this bit aborts the current operation in the following cases:
• Receiving a packet in Packet mode or in RX-Streaming mode
• Transmitting an ACK packet for a received frame during an Auto-Acknowledge operation
Out of scope
Note 1: Changes to most RX related settings must be only done when this bit is cleared.
2: Clear channel assessment (CSMAEN) and ACK-frame reception does not require RXEN = 1 as the
device turns the radio into RX when needed, irrespective of the status of the RXEN bit.
 2015 Microchip Technology Inc.
Preliminary
DS70005023C-page 203