MRF24XA_15 Datasheet, PDF (228/258 Pages) Microchip Technology – Low-Power, 2.4 GHz ISM-Band IEEE 802.15.4™ RF

MRF24XA
REGISTER 9-29:
bit 7
CFOMEAS (CFO MEASUREMENT INDICATION REGISTER)
R/W-00000000
CFOMEAS<7:0>
ADDRESS: 0x35
bit 0
Legend: R = Readable bit W = Writable bit
-n = Value at POR
‘1’ = Bit is set
r = Reserved
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
CFOMEAS<7:0>: CFO Measurement Field bits
If AFCOVR bit is cleared, then this register is written and valid when RXSFDIF is set with the value of
the Carrier Frequency Offset that was estimated during the acquisition of the packet. The host may use
this value together with the LQI as a preamble quality indication (the LQI is measured over the CFO
compensated payload).
If AFCOVR bit is set, this receiver compensates the Carrier Frequency Offset. Note that in this case,
the CFO estimation algorithm is disabled, thus ±13 ppm CFO is tolerated. CFORX has no effect when
AFCOVR is set.
Frequency Offset Unit is: ~1.62 ppm/LSB of the 2.4 GHz carrier. Two’s complement encoding is used.
9.12 Receive Status Vector (RSV)^{(1, 2)}
The Receive Status Vector (RSV) can extend the
received packet that gives extra information about the
link. RSV bits are individually enabled.
Note 1: RSV does not affect the LENGTH field of
the packet.
2: LQI, RSSI, CHDR and CFO are the order
of appending the CRC.
DS70005023C-page 228
Preliminary
 2015 Microchip Technology Inc.