MRF24XA_15 Datasheet, PDF (68/258 Pages) Microchip Technology – Low-Power, 2.4 GHz ISM-Band IEEE 802.15.4™ RF

MRF24XA
REGISTER 2-58: SFD4 (START FRAME DELIMITER PATTERN 4 CONFIGURATION REGISTER)
ADDRESS: 0x63
R/W-11100101
SFD4<7:0>
bit 7
bit 0
Legend: R = Readable bit W = Writable bit
-n = Value at POR
‘1’ = Bit is set
r = Reserved
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
SFD4<7:0>: Start Frame Delimiter Pattern 4 Register Field bits
This octet is used as SFD pattern with 250 kbps rate when proprietary MAC is in use. Otherwise, the
0xA7 pattern defined in the standard is used instead.
The hexadecimal digits must be different from 0x0 and from the corresponding digits in SFD<k>, where
k = 6 or 1, 2, 3. When OPTIMAL = 0, the value 0xA7 is forbidden.
REGISTER 2-59: SFD5 (START FRAME DELIMITER PATTERN 5 CONFIGURATION REGISTER)
ADDRESS: 0x64
R/W-01001101
SFD5<7:0>
bit 7
bit 0
Legend: R = Readable bit W = Writable bit
-n = Value at POR
‘1’ = Bit is set
r = Reserved
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
SFD5<7:0>: Start Frame Delimiter Pattern 5 Register Field bits
This octet is used as the MSB of the SFD pattern with 125 kbps rate.
DS70005023C-page 68
Preliminary
 2015 Microchip Technology Inc.