MRF24XA_15 Datasheet, PDF (221/258 Pages) Microchip Technology – Low-Power, 2.4 GHz ISM-Band IEEE 802.15.4™ RF

MRF24XA
REGISTER 9-20: SFD3 (START FRAME DELIMITER PATTERN 3 CONFIGURATION REGISTER)
ADDRESS: 0x62
R/W-00111011
SFD3<7:0>
bit 7
bit 0
Legend: R = Readable bit W = Writable bit
-n = Value at POR
‘1’ = Bit is set
r = Reserved
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
SFD3<7:0>: Start Frame Delimiter Pattern 3 Register Field bits
This octet is used as SFD pattern with 500 kbps rate.
When OPTIMAL = 0:
The hexadecimal digits must be different from 0x0 and different from the corresponding digits in
SFD<k>, k = 1, 2, 4, 6, and the value 0xA7 is forbidden.
When OPTIMAL = 1:
The hexadecimal digits must be different from 0x0.
REGISTER 9-21: SFD4 (START FRAME DELIMITER PATTERN 4 CONFIGURATION REGISTER)
ADDRESS: 0x63
R/W-11100101
SFD4<7:0>
bit 7
bit 0
Legend: R = Readable bit W = Writable bit
-n = Value at POR
‘1’ = Bit is set
r = Reserved
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
SFD4<7:0>: Start Frame Delimiter Pattern 4 Register Field bits
This octet is used as SFD pattern with 250 kbps rate when proprietary MAC is in use, otherwise, the
0xA7 pattern defined in the standard <1> is used instead.
The hexadecimal digits must be different from 0x0 and from the corresponding digits in SFD<k>, where,
k = 1, 2, 3, 6 when OPTIMAL = 0. The value 0xA7 is forbidden.
 2015 Microchip Technology Inc.
Preliminary
DS70005023C-page 221