MRF24XA_15 Datasheet, PDF (7/258 Pages) Microchip Technology – Low-Power, 2.4 GHz ISM-Band IEEE 802.15.4™ RF

MRF24XA
2.0 HARDWARE DESCRIPTION
2.1 Overview
MRF24XA is an IEEE 802.15.4 Standard compliant
2.4 GHz RF transceiver with extended feature set for
longer battery life, higher throughput and increased
operating range.
MRF24XA integrates the PHY and MAC functionality in
a single-chip solution. Figure 2-1 illustrates a block
diagram of the MRF24XA circuitry.
An external 16 MHz crystal clocks the frequency
synthesizer and generates a 2.4 GHz frequency RF
carrier.
The receiver is a zero-IF architecture consisting of a
Low-Noise Amplifier, down conversion mixers, channel
filters and baseband amplifiers with a Received Signal
Strength Indicator (RSSI).
The transmitter is a direct conversion architecture with
a 1 dBm maximum output (typical) and 20 dB power
control range.
The internal transmitter and receiver circuits contains
separate RFP and RFN input/output pins that
connects to impedance matching circuitry (balun) and
antenna. An external Power Amplifier or Low Noise
Amplifier, or both is controlled through the PA and
LNA pins.
Three general purpose Input/Output (GPIO) pins are
configurable for control or monitoring purposes.
The power management circuitry consists of an
integrated Low Dropout (LDO) voltage regulator and
a 5-bit resolution Battery Monitor Block. MRF24XA
is placed into a low-current (<40 nA typical) Deep
Sleep mode.
The Media Access Controller (MAC) circuitry can
sequence the transmit, receive and automatically
enable the security operations. The host MCU can
control these mechanisms through register
configurations and Frame Control (FCtrl) field
embedded in the downloaded formatted frames.
Three alternative frame formats are supported: IEEE
802.15.4 2003, 2006 compliant MAC frame formats
and a flexible and power-efficient advanced MAC
frame format, which is proprietary. Before launching
transmission, the host must load the buffer with a
formatted frame. The hardware can optionally perform
encryption and message integrity code appending as
configured, then sends the frame appending a Frame
Check Sequence (FCS).
Hardware can autonomously sequence acknowledge
reception and automatic retransmissions.
In reception, the format of the demodulated frame is
verified. Depending on the Configuration, duplicate
frames, frames with corrupted FCS or address
mismatch are discarded. On reception of valid frames,
automatic acknowledge sending, decryption and
message integrity checking are supported.
As the default, separate buffers are reserved for
transmission and reception. Alternatively, either the
Transmit Streaming (TX-Streaming) or the Receive
Streaming (RX-Streaming) modes are selected
whereby buffers are used by alternating between the
two for servicing a single direction of data flow. The
AES-128 engine are governed to perform network-
layer security processing and supports complete
security suites such as CTR, CBC-MAC and CCM*.
Transceiver is controlled through a 4-wire SPI,
interrupt and RESET pins.
2.2 Operating Modes
TABLE 2-1: MRF24XA POWER MODES
Table 2-1 summarizes the Operating modes of
MRF24XA.
Operating Mode
1.2V LDO
Internal Functional Blocks
Crystal
Oscillator
Synthesizer
RX Front
End
RX
Baseband
TX Chain
Deep Sleep
Sleep
RFOFF Crystal ON
RFOFF Synthesizer ON
RX Listen Power-Save
RX Listen
TX
OFF
ON
ON
ON
ON
ON
ON
OFF
OFF
ON
ON
ON
ON
ON
OFF
OFF
OFF
ON
ON
ON
ON
OFF
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
 2015 Microchip Technology Inc.
Preliminary
DS70005023C-page 7