MRF24XA_15 Datasheet, PDF (201/258 Pages) Microchip Technology – Low-Power, 2.4 GHz ISM-Band IEEE 802.15.4™ RF

MRF24XA
REGISTER 9-2: RXCON1 (MAC RECEIVE CONTROL 1 REGISTER) (CONTINUED)
ADDRESS: 0x15
bit 1
RSVCFOEN: Receive Status Vector CFO Enable bit
If bit is set, the estimated Carrier Frequency Offset of the received frame is appended after the
received frame in the packet buffer, using the same encoding as CFOMEAS register.
1 = Append CFO estimation
0 = Do not append estimated CFO
bit 0
Reserved: Maintain as ‘0’
REGISTER 9-3: TXCON (TRANSMIT CONTROL REGISTER)
R/W/HC -0
R/W-0
R/W/HC-0
R/HS/HC-1
R/W-1
TXST
DTSM
TXENC TXBUFEMPTY CSMAEN
bit 7
ADDRESS: 0x12
R/W-011
DR<2:0>
bit 0
Legend: R = Readable bit W = Writable bit
-n = Value at POR
‘1’ = Bit is set
r = Reserved
HC = Hardware Clear
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
HS = Hardware Set
bit 7
bit 6-0
TXST: Transmit Start bit. This is set or cleared by the host MCU bit^{(1, 2)}
1 = Starts the transmission of the next TX packet
0 = Termination of current TX operation, which may result in the transmission of an incomplete packet.
Hardware Clear:
• After the packet is successfully transmitted (including all attempted retransmissions, if any), the
hardware clears this bit and sets the TXIF and IDLEIF.
• If the packet transmission fails due to a CSMA failure, then this bit is cleared, and TXCSMAIF is
set.
• If Acknowledge is requested (AckReq bit field in the transmitted frame and AUTOACKEN register
bit are both set) and not received after the configured number of retransmissions (TXRETMCNT),
then TXST bit is cleared and a TXACKIF is set.
• In TX-Streaming mode (TRXMODE), TXST is set even when it is already set, resulting in a
“posted start”. When the current TX operation completes, the “posted start” immediately starts
afterward. Clearing of the TXST bit clears both the current and the posted (pending) TX starts.
TXOVFIF is unchanged when TXST = 1, a posted start is present and a Host Controller write to
the packet buffer occurs. Outside of TX-Streaming mode, writes to TXST when TXST is already
set is ignored.
Clearing this bit aborts the current operation in the following cases:
• When transmitting a packet in Packet mode or in TX-Streaming mode
• When waiting for an ACK packet after a transmission
• During the CSMA CA algorithm
• When transmitting a repeated frame
This field is read at any time to determine if the TX operation is in progress.
Out of scope
Note 1:
2:
Transmission may include automatic security processing, CRC appending, CSMA-CA channel access,
Acknowledge reception and retransmissions depending on the register Configuration and the Frame Control
field of the frame to be transmitted.
By setting the TXST bit in either Sleep/RFOFF state, the device transits to TX state for packet
transmission.
 2015 Microchip Technology Inc.
Preliminary
DS70005023C-page 201