MRF24XA_15 Datasheet, PDF (115/258 Pages) Microchip Technology – Low-Power, 2.4 GHz ISM-Band IEEE 802.15.4™ RF

MRF24XA
REGISTER 4-8:
R/W/HC/HS-0
RXEN
bit 7
RXCON1 (MAC RECEIVE CONTROL 1 REGISTER)
ADDRESS: 0x15
R/W-0
R/W/HC-0
R/W-1
R/W-1
R/W-1
R/W-1
R-0
NOPA
RXDEC RSVLQIEN RSVRSSIEN RSVCHDREN RSVCFOEN
r
bit 0
Legend: R = Readable bit W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
r = Reserved
HC = Hardware Clear
HS = Hardware Set
bit 7
RXEN: Receive Enable Field bit
This bit Enables/Disables the packet reception. If an RX packet is currently being received, clearing
this bit causes that packet to be discarded.
1 = RX enabled
0 = RX disabled
Hardware clear/set when:
• Cleared when TRXMODE is set to TX-Streaming mode
• Set when TRXMODE is set to RX-Streaming mode
Clearing this bit aborts the current operation in the following cases:
• Receiving a packet in Packet mode or in RX-Streaming mode
Changes to most RX related settings must be only done when this bit is cleared.
The clear channel assessment (CSMAEN) and ACK-frame reception does not require RXEN = 1 as the
device turns the radio into RX when needed, irrespective of the status of the RXEN bit.
bit 6
NOPA: No Parsing bit
This bit disables packet parsing. Only CRC is checked if it is enabled. This feature is useful in Sniffer
mode.
1 = Disable packet parsing
0 = Enable packet parsing
bit 5
RXDEC: RX Decryption bit
Setting this bit starts RX security processing (authentication or decryption, or both) on the last
received packet.
1 = RX security processing started/in process. RXDECIF or RXTAGIF is set.
0 = RX security processing inactive or complete
This bit clears itself after RX decryption is completed.
bit 4
RSVLQIEN: Receive Status Vector LQI Enable bit
If this bit is set, the measured Link Quality is appended after the received frame in the packet buffer.
1 = Append LQI field
0 = Do not append LQI field
bit 3
RSVRSSIEN: Receive Status Vector RSSI Enable bit
If this bit is set, the measured RSSI is appended after the received frame in the packet buffer.
1 = Append RSSI field
0 = Do not append RSSI field
bit 2
RSVCHDREN: Receive Status Vector Channel/MAC Type/Data Rate Enable bit
If this bit is set, Channel, MAC type and Data Rate configurations used with the received frame are
appended after the received frame in the packet buffer, using the encoding specified for CH<3:0>,
FRMFMT and DR<2:0> (concatenated in this order when most significant bit (MSb) is first).
1 = Append Channel, MAC type and Data Rate fields
0 = Do not append Channel, MAC type and Data Rate fields
bit 1
RSVCFOEN: Receive Status Vector CFO Enable bit
If this bit is set, the estimated Carrier Frequency Offset of the received frame is appended after the
received frame in the packet buffer, using the same encoding as CFOMEAS register.
1 = Append CFO estimation
0 = Do not append estimated CFO
bit 0
Reserved: Maintain as ‘0’
 2015 Microchip Technology Inc.
Preliminary
DS70005023C-page 115