PIC24FJ16MC101_12 Datasheet, PDF (68/350 Pages) Microchip Technology – 16-bit Microcontrollers (up to 32 KB Flash and 2 KB SRAM)

PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
6.4 External Reset (EXTR)
The external Reset is generated by driving the MCLR
pin low. The MCLR pin is a Schmitt trigger input with an
additional glitch filter. Reset pulses that are longer than
the minimum pulse width will generate a Reset. Refer
to Section 26.0 “Electrical Characteristics” for
minimum pulse width specifications. The External
Reset (MCLR) Pin (EXTR) bit in the Reset Control
register (RCON) is set to indicate the MCLR Reset.
6.4.1
EXTERNAL SUPERVISORY
CIRCUIT
Many systems have external supervisory circuits that
generate Reset signals to Reset multiple devices in the
system. This external Reset signal can be directly con-
nected to the MCLR pin to Reset the device when the
rest of system is Reset.
6.4.2 INTERNAL SUPERVISORY CIRCUIT
When using the internal power supervisory circuit to
Reset the device, the external Reset pin (MCLR)
should be tied directly or resistively to VDD. In this case,
the MCLR pin will not be used to generate a Reset. The
external Reset pin (MCLR) does not have an internal
pull-up and must not be left unconnected.
6.5 Software RESET Instruction (SWR)
Whenever the RESET instruction is executed, the
device will assert SYSRST, placing the device in a spe-
cial Reset state. This Reset state will not re-initialize the
clock. The clock source in effect prior to the RESET
instruction will remain. SYSRST is released at the next
instruction cycle, and the Reset vector fetch will
commence.
The Software Reset (Instruction) Flag bit (SWR) in the
Reset Control register (RCON<6>) is set to indicate the
software Reset.
6.6 Watchdog Time-out Reset (WDTO)
Whenever a Watchdog Time-out occurs, the device will
asynchronously assert SYSRST. The clock source will
remain unchanged. A WDT time-out during Sleep or
Idle mode will wake-up the processor, but will not reset
the processor.
The Watchdog Timer Time-out Flag bit (WDTO) in the
Reset Control register (RCON<4>) is set to indicate the
Watchdog Reset. Refer to Section 23.4 “Watchdog
Timer (WDT)” for more information on Watchdog
Reset.
6.7 Trap Conflict Reset
If a lower-priority hard trap occurs while a higher-prior-
ity trap is being processed, a hard trap conflict Reset
occurs. The hard traps include exceptions of priority
level 13 through level 15, inclusive. The address error
(level 13) and oscillator error (level 14) traps fall into
this category.
The Trap Reset Flag bit (TRAPR) in the Reset Control
register (RCON<15>) is set to indicate the Trap Conflict
Reset. Refer to Section 7.0 “Interrupt Controller” for
more information on trap conflict Resets.
6.8 Configuration Mismatch Reset
To maintain the integrity of the peripheral pin select
control registers, they are constantly monitored with
shadow registers in hardware. If an unexpected
change in any of the registers occur (such as cell dis-
turbances caused by ESD or other external events), a
configuration mismatch Reset occurs.
The Configuration Mismatch Flag bit (CM) in the Reset
Control register (RCON<9>) is set to indicate the con-
figuration mismatch Reset. Refer to Section 10.0 “I/O
Ports” for more information on the configuration
mismatch Reset.
Note:
The configuration mismatch feature and
associated Reset flag is not available on
all devices.
DS39997C-page 68
Preliminary
© 2011-2012 Microchip Technology Inc.