PIC24FJ16MC101_12 Datasheet, PDF (147/350 Pages) Microchip Technology – 16-bit Microcontrollers (up to 32 KB Flash and 2 KB SRAM)

PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
REGISTER 12-4: T5CON CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
TON⁽²⁾
—
TSIDL⁽¹⁾
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
U-0
—
TGATE⁽²⁾
TCKPS<1:0>⁽²⁾
—
bit 7
U-0
R/W-0
U-0
—
TCS⁽²⁾
—
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12-7
bit 6
bit 5-4
bit 3-2
bit 1
bit 0
TON: Timer5 On bit⁽²⁾
1 = Starts 16-bit Timer3
0 = Stops 16-bit Timer3
Unimplemented: Read as ‘0’
TSIDL: Stop in Idle Mode bit⁽¹⁾
1 = Discontinue timer operation when device enters Idle mode
0 = Continue timer operation in Idle mode
Unimplemented: Read as ‘0’
TGATE: Timer5 Gated Time Accumulation Enable bit⁽²⁾
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation enabled
0 = Gated time accumulation disabled
TCKPS<1:0>: Timer5 Input Clock Prescale Select bits⁽²⁾
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
Unimplemented: Read as ‘0’
TCS: Timer5 Clock Source Select bit⁽²⁾
1 = External clock from T5CK pin
0 = Internal clock (FOSC/2)
Unimplemented: Read as ‘0’
Note 1:
2:
When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (T4CON<3>), the TSIDL bit
must be cleared to operate the 32-bit timer in Idle mode.
When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control (T4CON<3>) register, these bits
have no effect.
Note: This register is available in PIC24FJ32MC101/102/104 devices only.
© 2011-2012 Microchip Technology Inc.
Preliminary
DS39997C-page 147