PIC24FJ16MC101_12 Datasheet, PDF (121/350 Pages) Microchip Technology – 16-bit Microcontrollers (up to 32 KB Flash and 2 KB SRAM)

PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
10.7 Peripheral Pin Select Registers
The PIC24FJ16MC101/102 and PIC24FJ32MC101/
102/104 family of devices implement 21 registers for
remappable peripheral configuration:
• Input Remappable Peripheral Registers (13)
• Output Remappable Peripheral Registers (8)
Note:
Input and Output Register values can only
be changed if OSCCON<IOLOCK> = 0.
See Section 10.4.3.1 “Control Register
Lock Sequence” for a specific command
sequence.
REGISTER 10-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
U-0
—
bit 15
U-0
U-0
R/W-1
R/W-1
R/W-1
—
—
INT1R<4:0>
R/W-1
R/W-1
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-8
bit 7-0
Unimplemented: Read as ‘0’
INT1R<4:0>: Assign External Interrupt 1 (INTR1) to the corresponding RPn pin
11111 = Input tied VSS
11110 = Reserved
.
.
.
11010 = Reserved
11001 = Input tied to RP25
.
.
.
00001 = Input tied to RP1
00000 = Input tied to RP0
Unimplemented: Read as ‘0’
© 2011-2012 Microchip Technology Inc.
Preliminary
DS39997C-page 121